Foundations — ARM architecture overview

5.1.6 · D1 · Hardware › Instruction Set Architecture (ISA) › ARM architecture overview

Isse pehle ki tum samjho kyun ARM woh choices karta hai jo karta hai, tumhe parent page par likha har word samajhna hoga ki woh actually kya hai. Yeh page har cheez ko zero se build karta hai — pehle plain words mein, phir ek picture, phir woh reason kyun ARM ko uski zaroorat hai. Upar se neeche padho; har idea agle ke liye ek brick hai.

Yeh ARM architecture overview ka foundation note hai. Pehle Hindi-English mein padhna chahte ho? Dekho 5.1.06 ARM architecture overview (Hinglish).

1. Bit — sabse chhota possible fact

Isko picture karo. Ek switch draw karo. Woh ya toh neeche hai (0) ya upar (1). Yahi bit ki poori duniya hai.

Yeh topic ko kyun chahiye. ARM jo kuch bhi karta hai — instructions, register contents, memory — woh ultimately sirf inhi switches ki rows hain. Jab parent note kehta hai "32-bit instruction," toh literally matlab hai 32 switches ki ek row.

2. Bits ko group karna — nibble, byte, word

Figure dekho. Neeche wali strip 8 switches = ek byte hai. Unhe chaar stack karo = 32 switches = ek word. Yeh 32 ka stack exactly ek ARM instruction ka saiz hai.

$2^4=162^8=2562^{32}\approx 4.3\times 10^9$

3. Hexadecimal — bits ke liye ek shorthand

Yeh kyun exist karta hai. 1110 0011 1010 0000 likhna error-prone hai. Ek hex digit = ek nibble, isliye 0xE3A0 wahi cheez hai, chaar guna chhoti. Jab parent note Thumb instruction ke liye 0x2001 likhta hai, toh bas yahi matlab hai "yeh 16 switches, 4-4 karke group kiye gaye."

4. Register — CPU ke andar ek chhota named box

Figure dekho. Left mein CPU hai jismein 16 labelled cubbyholes hain (r0–r15) — yeh registers hain, paas aur instant. Right mein bada memory wall hai, door. Parent note ka phrase "large register file" bas yahi matlab rakhta hai "bahut saare yeh cubbyholes."

Yeh topic ko kyun chahiye. ARM ek load-store machine hai: saari actual arithmetic inhi cubbyholes ke beech hoti hai. Isliye tumhe registers ko woh workbench soochna chahiye jahan saara kaam hota hai.

5. Memory aur address — numbered wall

Isko picture karo. Identical garon ki ek street. Har ghar ek byte hold karta hai; har ghar ka ek unique number hai. Register r1 mein number 1000 ho sakta hai, matlab "ghar number #1000 par jao." Notation [r1] ka matlab hai "woh memory box jiska address r1 ke andar hai" — square brackets ka matlab hai "yahan store kiye gaye address par jao."

Kyun registers ≠ memory. Registers desk par rakhe kuch boxes hain (pahunchne mein 1 cycle lagti hai). Memory shahr ke doosre end par ek warehouse hai (100+ cycles). Yahi doori poora reason hai kyun ARM unhe alag karta hai.

6. Instruction — ek order

Ek instruction mein ek mnemonic hota hai (ek chhota human naam) aur aksar operands (woh cheez jis par woh act karta hai):

ADD  r0, r1, r2   ; ADD mnemonic hai; r0,r1,r2 operands hain

Matlab: "r1 + r2 ko r0 mein daalo." Word mnemonic ka sirf yahi matlab hai "ek memory-aid naam" — humans ADD likhte hain, machine matching 32-bit pattern store karti hai.

Kaun se bits ka kya matlab hai ki details 5.1.07-ARM-instruction-encoding mein cover ki gayi hain. Yahan hume bas itna jaanna hai ki instruction hai 32 switches ki ek fixed row.

7. Program Counter (PC) aur +4

+4 kyun? Har ARMv7 instruction 4 bytes wide hai. Ek grab karne ke baad, unglee ko agle par slide karna hota hai, isliye:

$\text{PC}\leftarrow \text{PC}+4$

Parent note ka arrow $\text{PC}\stackrel{+4}{\to }\text{Next Instruction}$ exactly yahi hai: kyunki har instruction same 4-byte size hai, "next" hamesha "+4" hota hai, koi parsing nahi chahiye. (Thumb instructions 2 bytes ke hote hain, toh wahan +2 hota hai.)

8. Flags aur status register (N, Z, C, V)

Figure dekho. Ek CMP r0, #0 (r0 ko zero se compare karo) subtract karta hai aur answer phek deta hai, sirf flags rakhta hai. Agar r0 0 tha, toh Z flag light up karta hai. Agar negative tha, toh N flag light up karta hai.

Yeh topic ko kyun chahiye. Parent page par conditional execution (ADDGT, MOVLE) bas yahi hai ki CPU yeh flags dekhta hai aur decide karta hai ki instruction chalani hai ya nahi. Flags nahi → conditional execution nahi. Comparison ka har quadrant combinations se cover hota hai:

9. Immediate values aur # sign

Limit kyun matter karti hai. Kyunki poora instruction sirf 32 bits ka hai aur zyaadatar bits opcode aur registers ke liye use ho jaate hain, immediate ke liye sirf kuch bits bachte hain. Isliye tum koi bhi number store nahi kar sakte — sirf woh jo fit ho. Isliye parent page par Thumb ke "limited immediate values" hain: kam bits bache.

10. Pipeline — instructions ke liye ek assembly line

Figure dekho. Teen instructions belt par hain. Kisi bhi moment par ek fetch ho rahi hai, ek decode ho rahi hai, ek execute ho rahi hai. CPU roughly har cycle mein ek instruction finish karta hai chahe har ek belt par travel karne mein 3 cycles le.

Yeh topic ko kyun chahiye. Lagbhag har ARM design choice actually "pipeline ko smoothly flow karao" hai:

• Fixed-width instructions → aasaan Fetch.
• Load-store → predictable Execute timing (koi surprise memory stall nahi).
• Conditional execution → branch par belt flush karne se bacho.

Ek branch ek aisi instruction hai jo PC ko kahin aur jump kar deti hai. Ek flush belt par adhi-bani instructions ko phek dena hai kyunki CPU ne galat next address guess kiya. Gehra mechanics 5.2.03-pipelining mein hai.

11. RISC vs CISC — philosophy wala word

Ek line mein trade-off: RISC hardware ko simple banata hai aur software ko zyaada chhote steps karne deta hai; CISC hardware ko complex banata hai taaki programs chhote rahein. ARM ne simple hardware par bet lagayi — isliye yeh power kam peeta hai, jo seedha power optimization mein jaata hai.

Yeh foundations topic ko kaise feed karte hain

Har arrow ka matlab hai "left wala idea chahiye pehle, tabhi right wala samajh aata hai." Kisi bhi leaf se trace karo aur tum ARM par pahunch jaoge.

Equipment checklist

Apne aap ko test karo — right side cover karo aur oonchi awaaz mein jawab do.