Single-cycle datapath design: Visual walkthrough — Hardware deep dive

This is the picture-story of why a single-cycle CPU runs at the speed of its slowest instruction. We start from a bare wire and build up, one block at a time, until we can see the number $800 ps$ appear. Every symbol is drawn before it is used.

Parent: Single-cycle datapath design · Hinglish: 5.2.01 Single-cycle datapath design (Hinglish)

Step 1 — What "one clock cycle" actually means

WHAT. A clock is a wire that goes high–low–high–low forever, like a metronome tick. One full tick (low→high→next low→high edge... we count rising edge to rising edge) is the clock period, written $T_{c l k}$ , measured in picoseconds (ps, where $1 ps = 1 0^{- 12}$ seconds).

WHY. In a single-cycle machine, the rule is brutal: one instruction must fully finish inside one tick. So before we can compute a speed, we must agree on what a tick is and what "finish" means — the instruction's result must be settled and correct on the wires before the next rising edge grabs it.

PICTURE. The square wave below: the amber arrow marks one $T_{c l k}$ . Everything the instruction does must complete inside that amber span.

Step 2 — Data does not move instantly: block delay

WHAT. Every hardware block (a memory, the ALU, the register file) takes time to turn its inputs into correct outputs. We call that its propagation delay, written $t_{block}$ . Example: $t_{ALU} = 200 ps$ means "give the ALU stable inputs, and $200 ps$ later its output is correct."

WHY. If work were instantaneous, the clock could tick infinitely fast and this whole page would be pointless. The entire reason a clock has a minimum period is that real gates take real time. We need one number per block.

PICTURE. Signal enters the left of a block; the output on the right is wrong (grey, "settling") until $t_{block}$ has passed, then it snaps correct (cyan).

Term-by-term: $t_{I M e m}$ = read the instruction; $t_{R e g R e a d}$ = read registers; $t_{A LU}$ = compute; $t_{D M e m}$ = touch data memory; $t_{R e g W r i t e}$ = store the result. (See ALU design for where $t_{A LU}$ comes from.)

Step 3 — Delays on a wire ADD, not maximize

WHAT. When blocks are wired in series (output of one feeds input of the next), the total time is the sum of their delays. If block A takes $a$ and block B (after A) takes $b$ , the correct answer at B's output appears at time $a + b$ .

WHY. B cannot even begin settling until A's output is stable — B is staring at garbage until A finishes. So the delays stack end to end. This is addition, and it is the single most important operation on this whole page. (Contrast with the max we meet in Step 7 — that is for a different question.)

PICTURE. Two blocks in a chain; the time axis below shows A finishing at $a$ , then B running to $a + b$ . The amber bracket is the total.

Step 4 — Trace ONE instruction's route: `lw` (load word)

WHAT. lw $rt, off($rs) reads a word from memory into a register. Follow its signal from the moment the clock ticks:

Read the instruction — $t_{I M e m}$
Read register $rs (the base address) — $t_{R e g R e a d}$
ALU adds base + offset to form the memory address — $t_{A LU}$
Data memory reads that address — $t_{D M e m}$
Write the loaded word back into $rt — $t_{R e g W r i t e}$

WHY. lw is the instruction that touches every stage: both memories and a write-back. We trace it because whatever the slowest instruction is, lw is the prime suspect — its route is the longest.

PICTURE. The five blocks in a line, the cyan signal sweeping left→right, each hop labelled with its delay. Watch the running total on the amber ruler underneath.

Step 5 — Trace the OTHER instructions (every case)

WHAT. Different instruction types take different routes, so they skip some blocks. We must check them all — the reader must never hit an instruction we didn't trace.

R-type (add): read instr → read two registers → ALU → write back. No memory. $T_{R} = 200 + 100 + 200 + 0 + 100 = 600 ps$
sw (store): read instr → read registers → ALU (address) → write data memory. No write-back. $T_{s w} = 200 + 100 + 200 + 200 = 700 ps$
beq (branch): read instr → read registers → ALU compares (subtract, check zero). No memory, no write-back. $T_{b e q} = 200 + 100 + 200 = 500 ps$

WHY. Because the routes differ, so do the totals — and we cannot know the maximum until we've measured every competitor. Skipping one could hide the true slowest path.

PICTURE. Four horizontal bars, one per instruction type, length = its delay. lw is visibly the longest; beq the shortest.

Recall Which blocks does

sw skip, and why is it faster than lw? sw skips write-back ( $t_{R e g W r i t e}$ ) because a store produces no register result — it only writes memory. That's $700$ vs $800$ ps. It does NOT skip data memory (it writes it), so it's still slower than R-type.

Step 6 — The degenerate cases (never let a scenario surprise the reader)

WHAT. Two boundary situations:

A nop / do-nothing instruction still pays $t_{I M e m}$ to be fetched — you can never get below the fetch cost. So the minimum possible path is $t_{I M e m} = 200 ps$ , not zero.
What if two blocks had equal delay? The max (next step) just picks either — a tie is fine, no special handling. And if a block delay were $0$ (a plain wire), it simply drops out of the sum — no harm.

WHY. A design that "forgot" fetch would be nonsense; and a reader worrying about ties or zero-delay wires deserves an answer. These edges confirm the addition and max rules are total — defined for every input.

PICTURE. Left: the floor at $200 ps$ (fetch is unavoidable). Right: a tie between two bars, arrow showing max picks the shared height.

Step 7 — The single-cycle law: clock = the MAXIMUM route

WHAT. Here is the whole point. In a single-cycle machine, one clock period must fit the slowest instruction, because the same clock times all of them. So: $T_{c l k} \geq max_{instr} (t_{path of that instr}) = max (600, 700, 500, 800) = 800 ps$

Term-by-term: the $max (\dots)$ is asking "of all the instruction routes, which is longest?" — because if the clock were shorter than the longest route, that instruction would be grabbed before its answer settled → wrong result.

WHY use max and not sum or average? We are picking a single period that must be safe for the worst instruction, and worst = longest. An average would be too short for lw (corruption); a sum would be needlessly slow. max is exactly "safe for everyone, no slower than needed."

PICTURE. The four bars from Step 5, with a red dashed "clock line" dropped at the height of the tallest bar (lw). Every bar must fit under the line — and the wasted gap above the short bars is drawn in amber.

Step 8 — Stress test: add one slow instruction, watch it poison everyone

WHAT. Suppose we add mul whose ALU stage needs $500 ps$ instead of $200$ . Its route (R-type shape): $T_{m u l} = 200 + 100 + 500 + 100 = 900 ps$ Now $T_{c l k} \geq max (600, 700, 500, 800, 900) = 900 ps$ .

WHY. The max climbs the moment any single route grows. Because all instructions share that period, add, lw, beq — everyone — now runs at $900 ps$ , even though only mul needed it.

PICTURE. The Step 7 chart with a new, taller mul bar; the red clock line jumps up to $900$ , dragging the wasted amber gaps of every other bar even larger.

Recall One slow instruction, how much does it cost the fast

add? Before: add ran at $T_{c l k} = 800$ , wasting $800 - 600 = 200 ps$ . After adding mul: $T_{c l k} = 900$ , so add now wastes $900 - 600 = 300 ps$ — the fast instruction got slower without changing at all. That is the fundamental single-cycle disease.

The one-picture summary

The whole derivation in one frame: four routes of different length (Step 5), delays added along each route (Step 3), and the clock line set at the maximum (Step 7) — with the amber wasted gaps that motivate everything after this chapter.

Recall Feynman retelling — explain the whole walkthrough plainly

Think of four runners on four tracks of different lengths. Each runner's time is just adding up how long each stretch of their own track takes (Step 3–5). Now you must fire one finish-line gun that works for all four — you can't fire it before the slowest runner crosses, or you'd declare them "done" while they're still running (that's a wrong answer in hardware). So the gun waits for the longest track — the lw runner at $800 ps$ (Step 7). The three faster runners finish early and just stand around wasting time (the amber gaps). Add one very long track (mul at $900$ ), and now the gun waits even longer — and everyone stands around more (Step 8). That standing-around-waste is exactly the reason the next chapters invent Pipelining: keep the runners going but chop the track into equal short pieces so the gun can fire far more often.

Active-recall

Why do serial block delays add instead of taking a max?

A block can't start settling until its input (the previous block's output) is correct, so times stack end to end.

Why is the clock period set by the max over instructions, not the average?

One shared period must be safe for the worst (longest) route; anything shorter grabs a still-settling result → wrong answer.

lw delay with the given numbers?

200+100+200+200+100 = 800 ps.

R-type delay, and why less than lw?

600 ps — it skips data memory (no MEM stage).

Add mul needing 500 ps in the ALU: new clock period?

max(600,700,500,800,900) = 900 ps for every instruction.

What is the minimum possible instruction path, and why not zero?

t_IMem = 200 ps — every instruction must at least be fetched.