Single-cycle datapath design: Visual walkthrough — Hinglish deep dive

5.2.1 · D2 · Hardware › Processor Datapath & Pipelining › Single-cycle datapath design

Yeh ek picture-story hai is baat ki ki ek single-cycle CPU apni sabse slow instruction ki speed par kyun chalta hai. Hum ek bare wire se shuru karte hain aur ek-ek block add karte jaate hain, jab tak hum $800 ps$ ka number dekh nahi lete. Har symbol ko use karne se pehle draw kiya gaya hai.

Parent: Single-cycle datapath design · Hinglish: 5.2.01 Single-cycle datapath design (Hinglish)

Step 1 — "One clock cycle" ka matlab actually kya hai

KYA HAI. Ek clock ek wire hai jo hamesha high–low–high–low hoti rehti hai, jaise metronome ki tick. Ek poori tick (low→high→next low→high edge... hum rising edge se rising edge count karte hain) clock period hai, jise $T_{c l k}$ likhte hain, aur picoseconds (ps, jahan $1 ps = 1 0^{- 12}$ seconds) mein measure karte hain.

KYUN. Ek single-cycle machine mein rule bahut strict hai: ek instruction ko ek tick ke andar poori tarah finish ho jaana chahiye. Toh speed calculate karne se pehle, hum agree karte hain ki tick kya hoti hai aur "finish" ka matlab kya hai — instruction ka result next rising edge ke aane se pehle wires par settled aur correct hona chahiye.

PICTURE. Neeche square wave hai: amber arrow ek $T_{c l k}$ mark karta hai. Jo bhi instruction karta hai woh sab us amber span ke andar complete ho jaana chahiye.

Step 2 — Data instantly move nahi karta: block delay

KYA HAI. Har hardware block (ek memory, ALU, register file) ko apne inputs se correct outputs banane mein time lagta hai. Hum ise propagation delay kehte hain, jise $t_{block}$ likhte hain. Example: $t_{ALU} = 200 ps$ matlab hai "ALU ko stable inputs do, aur $200 ps$ baad uski output correct hogi."

KYUN. Agar kaam instantaneous hota, toh clock infinitely fast tick kar sakta tha aur yeh poora page pointless hota. Clock ka minimum period hone ki poori wajah yeh hai ki real gates ko real time lagta hai. Hume har block ke liye ek number chahiye.

PICTURE. Signal block ke left se enter karta hai; right par output tab tak galat hai (grey, "settling") jab tak $t_{block}$ nahi guzar jaata, phir woh correct ho jaata hai (cyan).

Term-by-term: $t_{I M e m}$ = instruction read karo; $t_{R e g R e a d}$ = registers read karo; $t_{A LU}$ = compute karo; $t_{D M e m}$ = data memory touch karo; $t_{R e g W r i t e}$ = result store karo. ( $t_{A LU}$ kahan se aata hai, yeh dekhne ke liye ALU design dekho.)

Step 3 — Wire par delays ADD hote hain, maximize nahi

KYA HAI. Jab blocks series mein wire hote hain (ek ka output doosre ka input ban jaata hai), total time unke delays ka sum hota hai. Agar block A $a$ time leta hai aur block B (A ke baad) $b$ time leta hai, toh B ke output par sahi answer time $a + b$ par aata hai.

KYUN. B tab tak settle bhi nahi shuru kar sakta jab tak A ka output stable na ho — A finish hone tak B kachra dekh raha hota hai. Isliye delays end to end stack hote hain. Yeh addition hai, aur yeh is poore page par sabse important operation hai. (Step 7 mein jo max milta hai usse compare karo — woh ek alag sawaal ke liye hai.)

PICTURE. Ek chain mein do blocks; neeche time axis dikhata hai A $a$ par finish karta hai, phir B $a + b$ tak chalta hai. Amber bracket total hai.

Step 4 — EK instruction ka route trace karo: `lw` (load word)

KYA HAI. lw $rt, off($rs) memory se ek word register mein read karta hai. Clock tick karne ke moment se signal follow karo:

Instruction read karo — $t_{I M e m}$
Register $rs (base address) read karo — $t_{R e g R e a d}$
ALU base + offset add karke memory address banata hai — $t_{A LU}$
Data memory us address ko read karti hai — $t_{D M e m}$
Loaded word $rt mein wapas write karo — $t_{R e g W r i t e}$

KYUN. lw woh instruction hai jo har stage ko touch karta hai: dono memories aur write-back. Hum ise trace karte hain kyunki jo bhi slowest instruction hai, lw prime suspect hai — iska route sabse lamba hai.

PICTURE. Paanch blocks ek line mein, cyan signal left→right sweep karta hai, har hop uski delay ke saath labelled hai. Neeche amber ruler par running total dekho.

Step 5 — BAAKI instructions trace karo (har case)

KYA HAI. Alag instruction types alag routes lete hain, isliye woh kuch blocks skip karte hain. Hume sab check karne chahiye — reader ko koi aisi instruction nahi milni chahiye jo humne trace na ki ho.

R-type (add): instr read karo → do registers read karo → ALU → write back. Koi memory nahi. $T_{R} = 200 + 100 + 200 + 0 + 100 = 600 ps$
sw (store): instr read karo → registers read karo → ALU (address) → data memory mein likho. Koi write-back nahi. $T_{s w} = 200 + 100 + 200 + 200 = 700 ps$
beq (branch): instr read karo → registers read karo → ALU compare karta hai (subtract, zero check karo). Koi memory nahi, koi write-back nahi. $T_{b e q} = 200 + 100 + 200 = 500 ps$

KYUN. Kyunki routes alag hain, totals bhi alag hain — aur maximum tab tak nahi pata chalta jab tak hum har competitor ko measure na kar lein. Ek ko skip karna sabse slow path ko chupa sakta hai.

PICTURE. Char horizontal bars, har instruction type ke liye ek, length = uski delay. lw visibly sabse lamba hai; beq sabse chhota.

Recall

sw kaun se blocks skip karta hai, aur woh lw se faster kyun hai? sw write-back ( $t_{R e g W r i t e}$ ) skip karta hai kyunki store koi register result produce nahi karta — yeh sirf memory mein likhta hai. Yeh $700$ vs $800$ ps hai. Yeh data memory skip nahi karta (woh ise likhta hai), isliye yeh R-type se phir bhi slow hai.

Step 6 — Degenerate cases (kabhi koi scenario reader ko surprise mat karne do)

KYA HAI. Do boundary situations:

Ek nop / do-nothing instruction phir bhi fetch hone ke liye $t_{I M e m}$ pay karta hai — fetch cost se neeche kabhi nahi ja sakte. Isliye minimum possible path $t_{I M e m} = 200 ps$ hai, zero nahi.
Agar do blocks ki equal delay ho toh? max (next step) kisi bhi ek ko pick kar leta hai — tie theek hai, koi special handling nahi. Aur agar kisi block ki delay $0$ ho (ek plain wire), toh woh simply sum se nikal jaata hai — koi nuksaan nahi.

KYUN. Ek design jo "fetch bhool gaya" nonsense hoga; aur ties ya zero-delay wires ke baare mein sochne wala reader ek answer ka haqdar hai. Yeh edges confirm karte hain ki addition aur max rules total hain — har input ke liye defined hain.

PICTURE. Left: $200 ps$ par floor (fetch unavoidable hai). Right: do bars ke beech tie, arrow dikhata hai max shared height pick karta hai.

Step 7 — Single-cycle law: clock = MAXIMUM route

KYA HAI. Yahi poora point hai. Single-cycle machine mein, ek clock period sabse slow instruction ke liye fit hona chahiye, kyunki wahi clock sab ko time karta hai. Isliye: $T_{c l k} \geq max_{instr} (t_{path of that instr}) = max (600, 700, 500, 800) = 800 ps$

Term-by-term: $max (\dots)$ pooch raha hai "saari instruction routes mein se kaun si sabse lambi hai?" — kyunki agar clock sabse lambe route se chhoti hoti, toh woh instruction apna answer settle hone se pehle grab ho jaati → galat result.

max kyun use karte hain, sum ya average kyun nahi? Hum ek aisi single period choose kar rahe hain jo worst instruction ke liye safe ho, aur worst = longest. Average lw ke liye bahut chhoti hogi (corruption); sum unnecessarily slow hogi. max exactly hai "sabke liye safe, zaroorat se zyada slow nahi."

PICTURE. Step 5 ke char bars, red dashed "clock line" sabse unche bar (lw) ki height par rakh di gayi hai. Har bar line ke neeche fit hona chahiye — aur chhote bars ke upar wasted amber gap draw kiya gaya hai.

Step 8 — Stress test: ek slow instruction add karo, dekho yeh sabko kaise poison karta hai

KYA HAI. Maano hum mul add karte hain jiska ALU stage $200$ ki jagah $500 ps$ leta hai. Uska route (R-type shape): $T_{m u l} = 200 + 100 + 500 + 100 = 900 ps$ Ab $T_{c l k} \geq max (600, 700, 500, 800, 900) = 900 ps$ .

KYUN. max tab badhta hai jab koi bhi ek route grow kare. Kyunki saari instructions woh period share karti hain, add, lw, beq — sab — ab $900 ps$ par chalte hain, chahe sirf mul ko hi yeh chahiye tha.

PICTURE. Step 7 chart mein ek nayi, unchi mul bar hai; red clock line $900$ tak jump karti hai, baaki har bar ke wasted amber gaps aur bade ho jaate hain.

Recall Ek slow instruction, fast

add ko kitna cost karta hai? Pehle: add $T_{c l k} = 800$ par chalta tha, $800 - 600 = 200 ps$ waste karta tha. mul add karne ke baad: $T_{c l k} = 900$ , toh add ab $900 - 600 = 300 ps$ waste karta hai — fast instruction bina kuch change hue slow ho gayi. Yahi fundamental single-cycle disease hai.

Ek-picture summary

Ek frame mein poori derivation: alag length ke char routes (Step 5), delays har route ke saath add hote hain (Step 3), aur clock line maximum par set hoti hai (Step 7) — amber wasted gaps ke saath jo is chapter ke baad sab kuch motivate karte hain.

Recall Feynman retelling — poora walkthrough seedha explain karo

Char alag-alag length ke tracks par char runners ke baare mein socho. Har runner ka time bas yeh hai ki unke apne track ke har stretch mein kitna time lagta hai, woh sab add karte jao (Step 3–5). Ab tumhe ek finish-line gun chalani hai jo charon ke liye kaam kare — tum ise tab tak nahi chala sakte jab tak sabse slow runner cross na kar le, warna tum unhe "done" declare kar doge jab woh abhi bhi daud rahe hain (hardware mein woh galat answer hai). Isliye gun sabse lambe track ka wait karti hai — lw runner $800 ps$ par (Step 7). Teen fast runners pehle finish kar lete hain aur bas idhar-udhar khade rehte hain time waste karte hue (amber gaps). Ek bahut lamba track add karo (mul $900$ par), aur ab gun aur zyada wait karti hai — aur sab aur zyada khade rehte hain (Step 8). Woh khade-rehne-ka-waste exactly woh reason hai ki agli chapters Pipelining kyun invent karti hain: runners ko chalate raho lekin track ko equal chhote pieces mein kaato taaki gun bahut zyada baar fire kar sake.

Active-recall

Serial block delays max karne ki bajay add kyun hote hain?

Ek block tab tak settle shuru nahi kar sakta jab tak uska input (pichle block ka output) correct na ho, isliye times end to end stack hote hain.

Clock period instructions par max se kyun set hoti hai, average se kyun nahi?

Ek shared period worst (longest) route ke liye safe honi chahiye; kuch bhi chhota ek abhi-bhi-settling result grab karta hai → galat answer.

Diye gaye numbers se lw delay?

200+100+200+200+100 = 800 ps.

R-type delay, aur lw se kam kyun?

600 ps — yeh data memory skip karta hai (koi MEM stage nahi).

mul add karo jise ALU mein 500 ps chahiye: naya clock period?

max(600,700,500,800,900) = 900 ps har instruction ke liye.

Minimum possible instruction path kya hai, aur kyun zero nahi?

t_IMem = 200 ps — har instruction ko kam se kam fetch toh hona hi padta hai.