Question bank — Single-cycle datapath design

False — it means each instruction finishes in one clock cycle (CPI = 1); all instruction types coexist and muxes route the data appropriately.

False — total time is CPI × clock period × instruction count, and single-cycle pays for CPI = 1 with an enormous clock period set by the slowest instruction.

False — within the same cycle the ALU is already busy with the instruction's own arithmetic, so PC+4 and the branch target each need their own dedicated adder.

True in the sense that the wires and blocks are all present and powered every cycle, but unused results (e.g. data memory for an R-type) are simply ignored by the control signals rather than removed. These are hardware regions, not five clock cycles.

False — the clock period is the max over all instructions, so one slow instruction raises the period for every instruction on the machine.

True — the register file always reads rs and rt in the decode region regardless of the outcome; only the use of the comparison (the PCSrc mux) changes.

False — if RegWrite = 0 nothing is written, so the destination-select mux is a "don't care" (X); its value is irrelevant because no write happens.

False — branches also sign-extend their 16-bit offset to 32 bits (so negative backward jumps work) before the left-shift by 2.

False — a jump is unconditional; it ignores Zero entirely and always overrides the PC with its computed target via a dedicated jump-target mux.

Order is wrong — you must sign-extend first, then shift left 2; shifting first corrupts the high bits and destroys sign correctness for negative offsets.

The base is wrong — it must be PC+4, the already-incremented PC, not PC; MIPS defines branches relative to the next instruction.

Incomplete — it needs Branch AND the ALU's Zero output; a branch instruction that compares unequal must not take the branch.

Wrong value — a load must write back the data-memory output, so MemToReg = 1 selects memory (the ALU here only computed the address).

Wrong — R-type has no immediate; ALUSrc = 0 so the ALU's second operand is the register rt. ALUSrc = 1 is for lw/sw.

The premise is the whole point — R-type writes rd (bits 15–11) and I-type writes rt (bits 20–16); they disagree, which is exactly why the mux must exist.

Misleading — sw writes no register, so MemToReg is a don't-care (X); assigning it a definite value isn't wrong but implies a meaning that isn't there.

Wrong statistic — it must equal the maximum (worst-case) instruction delay, because a single fixed clock must satisfy even the slowest instruction.

Wrong — a jump takes the 26-bit target, shifts it left 2, and concatenates the top 4 bits of PC+4 (PC[31:28]) to fill out 32 bits; it is not a sign-extended PC-relative offset.

Because instruction types disagree on that input — R-type wants a register value, while load/store/immediate want the sign-extended immediate; a mux (controlled by ALUSrc) resolves the disagreement.

Neither produces a value destined for a register, so writing would overwrite a register with garbage and silently corrupt program state.

It touches every region — instruction memory, register read, ALU (address), data memory, and register write-back — so its delay chain is the longest.

The offset is counted in instructions (words), and each instruction is 4 bytes, so multiplying by 4 (shift left 2) converts word-count into a byte address.

Every instruction shares one fixed clock period set by the slowest instruction, so the add finishes early and then just wastes the remaining time.

Because when an instruction doesn't perform an action (e.g. doesn't write a register), the signals feeding that action have no effect, so their value is free to be anything.

In multi-cycle the ALU is used in different cycles for different jobs, so it can be time-shared; single-cycle crams everything into one cycle, leaving no free moment. See Multi-cycle datapath.

Pipelining keeps CPI near 1 while slashing the clock period (each stage's short delay, not the whole instruction's), so overall time drops. See Pipelining.

Because the PC now has three possible next values — PC+4, branch target, and jump target — and the branch PCSrc mux only picks between two, so a second (jump) mux is added to override with the jump target.

Nothing useful — MemRead and MemWrite are both 0, so any output is ignored; the block is physically present but electrically idle for this instruction.

It's dead — RegWrite = 0, so whatever appears on the write-back wires and destination mux is discarded; the register file is left untouched.

No — PCSrc needs Branch AND Zero; with Branch = 0 (a non-branch instruction) the Zero output is irrelevant and PC advances by PC+4.

There is none — a store writes memory, not a register, so the entire destination-select logic is a don't-care.

Either — the clock equals the shared maximum, so both are on the critical path and the period is that common value.

It's a valid degenerate case — the sign-extended zero adds nothing, so the ALU computes the base register's address directly; the datapath behaves identically, just with offset 0.

No — sign-extension turns the negative 16-bit offset into a correct negative 32-bit value, and the same adder produces a smaller target address; the geometry of the path is unchanged.

No — its next-PC comes purely from the instruction's own target bits plus PC[31:28]; register reads still happen physically but their outputs are ignored, and the ALU/Zero results play no role in the jump decision.