Single-cycle datapath design: Question bank — Hinglish deep dive

5.2.1 · D5 · Hardware › Processor Datapath & Pipelining › Single-cycle datapath design

Shuru karne se pehle, ensure karo ke yeh words solid lagte hain; agar nahi, toh parent note dobara dekho. Neeche diya figure tumhara map hai — har question kisi block ya wire ko refer karta hai, toh jab bhi koi naam unfamiliar lage, wapis glance karo.

Recall Quick vocabulary refresh — hardware blocks (sirf tab kholo agar unsure ho)

PC (Program Counter) ::: ek chhota register jo us instruction ka address hold karta hai jo abhi run ho rahi hai; har cycle ya toh PC+4 pe advance hota hai (agli instruction, 4 bytes aage) ya branch/jump target pe jump karta hai.
Instruction memory ::: woh storage jahan se CPU current instruction padhta hai, PC mein held address use karke.
Data memory ::: alag storage jahan se lw (load) read karta hai aur sw (store) likhta hai; ordinary arithmetic kabhi isko touch nahi karti.
Register file ::: CPU registers ka chhota fast bank jisme do read ports aur ek write port hote hain.
ALU (Arithmetic Logic Unit) ::: woh block jo add, subtract, compare, aur memory addresses compute karta hai — datapath ka "calculator".
Sign-extender ::: hardware jo ek 16-bit immediate ki top bit ko upar copy karta hai taaki ek sahi 32-bit value bane (negatives ko negative rakhta hai).

Recall Quick vocabulary refresh — control signals (sirf tab kholo agar unsure ho)

RegWrite ::: 1 = is cycle mein register file mein result likho; 0 = register file ko untouched chhodo.
ALUSrc ::: ALU ka doosra input choose karta hai — 0 = register rt, 1 = sign-extended immediate.
MemRead / MemWrite ::: data memory se reading enable / data memory mein writing enable karta hai (1 = active).
MemToReg ::: write-back value choose karta hai — 0 = ALU result, 1 = data-memory output.
RegDst ::: destination register field choose karta hai — 0 = rt (I-type), 1 = rd (R-type).
Branch ::: sirf branch instructions ke liye 1 hota hai; next PC decide karne ke liye Zero ke saath combine hota hai.
Zero ::: ALU se ek output jo 1 hoti hai jab uska result zero ho (used to test beq equality).
PCSrc ::: next PC choose karta hai — 0 = PC+4, 1 = branch target; Branch AND Zero se drive hota hai.

Recall Quick vocabulary refresh — general terms (sirf tab kholo agar unsure ho)

CPI ::: cycles per instruction — ek instruction average mein kitne clock ticks leta hai.
Critical path ::: hardware delays ki sabse lambi chain jo kisi bhi instruction ko ek cycle mein traverse karni padti hai.
Mux ::: ek selector switch; yeh kai input wires mein se ek ko pass through karne ke liye choose karta hai, ek control signal ke zariye.
R-type / I-type / J-type ::: instruction ke shapes. R-type (add) sirf registers use karta hai; I-type (lw, sw, beq) ek 16-bit immediate carry karta hai; J-type (j) ek 26-bit jump target carry karta hai aur unconditionally PC change karta hai.

True ya false — justify karo

TF1. "Single-cycle" ka matlab hai CPU sirf ek type ki instruction run kar sakta hai.

False — iska matlab hai har instruction ek clock cycle mein khatam hoti hai (CPI = 1); sabhi instruction types ek saath exist karti hain aur muxes data ko appropriately route karte hain.

TF2. Kyunki CPI = 1 hai, single-cycle CPU automatically sabse fast possible design hai.

False — total time CPI × clock period × instruction count hoti hai, aur single-cycle CPI = 1 ke liye ek bahut bada clock period pay karta hai jo sabse slow instruction se set hota hai.

TF3. Single-cycle datapath mein ALU ko PC+4 compute karne ke liye reuse kiya ja sakta hai.

False — usi cycle mein ALU pehle se instruction ki apni arithmetic se busy hai, isliye PC+4 aur branch target dono ko apne dedicated adder chahiye.

TF4. Har instruction physically har cycle mein saare paanch functional-unit regions se guzarti hai.

True is sense mein ki wires aur blocks har cycle present aur powered hain, lekin unused results (jaise R-type ke liye data memory) control signals ki wajah se simply ignore ho jaate hain, remove nahi hote. Yeh hardware regions hain, paanch clock cycles nahi.

TF5. Ek slow instruction add karna sirf us instruction ko slow karta hai.

False — clock period sabhi instructions ke maximum pe set hoti hai, isliye ek slow instruction har instruction ka period poori machine pe raise kar deti hai.

TF6. Ek beq jo taken nahi hai woh phir bhi register file read karta hai.

True — register file hamesha decode region mein rs aur rt read karti hai chahe outcome kuch bhi ho; sirf comparison ka use (PCSrc mux) change hota hai.

TF7. Store ke liye RegWrite = 0 set karna RegDst mux ko bhi sahi set karne ki zaroorat hai.

False — agar RegWrite = 0 hai toh kuch likha nahi jaata, isliye destination-select mux ek "don't care" (X) hai; uski value irrelevant hai kyunki koi write hoti hi nahi.

TF8. Sign-extender sirf arithmetic immediates ke liye zaroori hai, branches ke liye nahi.

False — branches bhi apna 16-bit offset 32 bits tak sign-extend karte hain (taaki negative backward jumps kaam karein) left-shift by 2 se pehle.

TF9. J-type jump (j) jump karne ka faisla karne ke liye ALU ke Zero output ka use karta hai.

False — jump unconditional hota hai; yeh Zero ko poori tarah ignore karta hai aur hamesha ek dedicated jump-target mux ke zariye PC ko apne computed target se override karta hai.

Error dhundho

SE1. "Branch ke liye, 16-bit immediate ko 2 se left shift karo, phir 32 bits tak sign-extend karo."

Order galat hai — pehle sign-extend karna chahiye, phir 2 se left shift; pehle shift karna high bits corrupt kar deta hai aur negative offsets ke liye sign correctness destroy kar deta hai.

SE2. "Branch target = PC + (SignExt(imm) << 2)."

Base galat hai — yeh PC+4 hona chahiye, pehle se increment hua PC, PC nahi; MIPS branches ko agli instruction ke relative define karta hai.

SE3. "PCSrc mux sirf Branch signal se control hota hai."

Incomplete hai — Branch AND ALU ke Zero output dono chahiye; ek branch instruction jo unequal compare kare use branch nahi lena chahiye.

SE4. "lw ke liye, MemToReg = 0 taaki ALU result write back ho."

Galat value hai — load ko data-memory output write back karna chahiye, isliye MemToReg = 1 memory select karta hai (ALU ne yahan sirf address compute kiya tha).

SE5. "R-type ko ALUSrc = 1 chahiye taaki immediate ALU mein feed ho."

Galat hai — R-type mein koi immediate nahi hota; ALUSrc = 0 hota hai isliye ALU ka doosra operand register rt hota hai. ALUSrc = 1 lw/sw ke liye hai.

SE6. "Agar sabhi instructions same destination field use karein toh RegDst mux drop kar sakte hain."

Premise hi poora point hai — R-type rd (bits 15–11) mein likhta hai aur I-type rt (bits 20–16) mein; woh disagree karte hain, yahi exact reason hai ki mux exist karna chahiye.

SE7. "sw MemToReg = 0 set karta hai safe rehne ke liye."

Misleading hai — sw koi register nahi likhta, isliye MemToReg don't-care (X) hai; isko ek definite value assign karna galat nahi hai lekin yeh ek aisi meaning imply karta hai jo wahan hai hi nahi.

SE8. "Clock period average instruction delay ke barabar honi chahiye."

Galat statistic hai — yeh maximum (worst-case) instruction delay ke barabar honi chahiye, kyunki ek fixed clock ko sabse slow instruction bhi satisfy karni padti hai.

SE9. "J-type jump target sirf SignExt(imm) << 2 hai, exactly branch jaisi."

Galat hai — jump 26-bit target leta hai, use 2 se left shift karta hai, aur 32 bits complete karne ke liye PC+4 ke top 4 bits (PC[31:28]) ko concatenate karta hai; yeh sign-extended PC-relative offset nahi hai.

Why questions

WHY1. ALU ke doosre input par mux kyun hota hai?

Kyunki instruction types us input par disagree karti hain — R-type ko register value chahiye, jabki load/store/immediate ko sign-extended immediate chahiye; ek mux (ALUSrc se controlled) is disagreement ko resolve karta hai.

WHY2. sw aur beq ke liye RegWrite = 0 kyun hona chahiye?

Koi bhi register ke liye koi value produce nahi karta, isliye likhna ek register ko garbage se overwrite kar deta aur silently program state corrupt kar deta.

WHY3. MIPS single-cycle mein lw usually critical path kyun hota hai?

Yeh har region ko touch karta hai — instruction memory, register read, ALU (address), data memory, aur register write-back — isliye uski delay chain sabse lambi hoti hai.

WHY4. Branch offset ko bytes mein convert karne ke liye 2 se left-shift kyun zaroori hai?

Offset instructions (words) mein count hota hai, aur har instruction 4 bytes ki hoti hai, isliye 4 se multiply karna (2 se left shift) word-count ko byte address mein convert karta hai.

WHY5. Ek fast add single-cycle mein slow kyun force hota hai?

Har instruction ek fixed clock period share karta hai jo sabse slow instruction se set hota hai, isliye add jaldi khatam ho jaata hai aur phir bacha hua waqt waste karta hai.

WHY6. Control truth table mein "don't care" (X) entries kyun appear karti hain?

Kyunki jab ek instruction koi action perform nahi karti (jaise koi register nahi likhti), toh us action ko feed karne wale signals ka koi effect nahi hota, isliye unki value kuch bhi ho sakti hai.

WHY7. Multi-cycle designs ALU ko PC+4 ke liye reuse kar sakte hain lekin single-cycle nahi kar sakta — kyun?

Multi-cycle mein ALU alag cycles mein alag jobs ke liye use hota hai, isliye time-share kiya ja sakta hai; single-cycle sab kuch ek cycle mein cramm karta hai, koi free moment nahi bachta. Dekho Multi-cycle datapath.

WHY8. Pipelining single-cycle ko kyun beat karta hai jabki dono ka CPI ≈ 1 hai?

Pipelining CPI near 1 rakhte hue clock period bhi ghata deta hai (har stage ki short delay, poori instruction ki nahi), isliye overall time kam ho jaati hai. Dekho Pipelining.

WHY9. J-type jump ko PC input par apna alag extra mux kyun chahiye?

Kyunki PC ke paas ab teen possible next values hain — PC+4, branch target, aur jump target — aur branch PCSrc mux sirf do ke beech choose karta hai, isliye ek doosra (jump) mux add kiya jaata hai jump target se override karne ke liye.

Edge cases

EC1. R-type instruction ke dauran data memory kya karta hai?

Kuch useful nahi — MemRead aur MemWrite dono 0 hain, isliye koi bhi output ignore ho jaata hai; block physically present hai lekin is instruction ke liye electrically idle hai.

EC2. sw ke liye write-back path ka kya hota hai?

Woh dead hai — RegWrite = 0 hai, isliye write-back wires aur destination mux par jo bhi appear ho woh discard ho jaata hai; register file untouched rehti hai.

EC3. Agar branch ke ALU comparison se Zero = 1 mile lekin Branch signal 0 ho, toh kya branch taken hai?

Nahi — PCSrc ko Branch AND Zero chahiye; Branch = 0 ke saath (ek non-branch instruction) Zero output irrelevant hai aur PC PC+4 se advance karta hai.

EC4. Store instruction ka destination register kya hai?

Koi nahi hai — store memory mein likhta hai, register mein nahi, isliye poori destination-select logic don't-care hai.

EC5. Agar do instructions ki equal maximum delay ho, toh clock kaunsa set karta hai?

Koi bhi — clock shared maximum ke equal hoti hai, isliye dono critical path par hain aur period woh common value hai.

EC6. lw ke liye immediate zero ho toh kya hoga?

Yeh ek valid degenerate case hai — sign-extended zero kuch add nahi karta, isliye ALU seedha base register ka address compute karta hai; datapath exactly waise hi behave karta hai, sirf offset 0 ke saath.

EC7. Kya ek taken backward branch (negative offset) ke liye special hardware chahiye?

Nahi — sign-extension negative 16-bit offset ko ek correct negative 32-bit value mein turn karta hai, aur wahi adder ek chhota target address produce karta hai; path ki geometry unchanged rehti hai.

EC8. Kya J-type jump kabhi register file read karta hai ya ALU result use karta hai?

Nahi — uska next-PC purely instruction ke apne target bits plus PC[31:28] se aata hai; register reads physically hoti rehti hain lekin unke outputs ignore ho jaate hain, aur ALU/Zero results jump decision mein koi role nahi nibhaate.