Single-cycle datapath design: Foundations — Hinglish deep dive

5.2.1 · D1 · Hardware › Processor Datapath & Pipelining › Single-cycle datapath design

Isse pehle ki tum single-cycle datapath note padh sako, tumhe har woh symbol khud se samajh aana chahiye jo woh tumhare samne phenkta hai. Neeche, har idea ko kuch nahi se build kiya gaya hai, usse ek picture di gayi hai, aur us ek sawaal se justify kiya gaya hai jo woh answer karta hai. Upar se neeche padho — seedhi ke har paaydaan ko uske neeche waale ki zaroorat hai.

1. Ek bit, ek wire, aur ek number

32 wires ko side by side rakho aur tum ek number spell kar sakte ho. Humein yeh agree karna hai ki kaun si wire kitne ke liye count hoti hai.

Figure 1 — yeh padho: upar ke aath chhote boxes single-bit wires hain jinhe unki place values se label kiya gaya hai; neeche ki moti laal arrow wahi information hai jo ek 32-bit bus ke roop mein carry ki ja rahi hai. Yeh seekho: "ek moti arrow with slash aur 32 = battees wires saath mein travel kar rahi hain."

Topic ko iske zaroorat kyun hai: datapath mein har box — ALU, memories, register file — 32-bit words mein baat karta hai. Jab parent note ALU mein ek arrow draw karta hai, woh arrow actually 32 wires hain.

2. Registers aur register file

Parent note mein register file ke do read ports aur ek write port hain:

Ek read port = ek lookup: "yeh lo ek 5-bit register number, mujhe iska 32-bit value do." Do ports humein ek saath do operands padhne dete hain (jaise add ko do inputs chahiye).
Ek write port = ek store: "yeh lo ek register number aur ek value; agle bell par, value wahan rakho." Yeh tabhi kaam karta hai jab RegWrite control wire 1 ho.

Figure 2 — yeh padho: baayein do kaalee arrows (rs, rt) andar jaati hain, daayein do kaalee arrows (read data 1, read data 2) bahar aati hain — yeh do read ports hain. Neeche ki laal arrow single write port hai, aur yeh tabhi data move karta hai jab RegWrite = 1 ho. Seekho: padhna hamesha allowed hai; likhne ke liye permission chahiye.

Topic ko iske zaroorat kyun hai: rs, rt, rd, RegWrite, aur "write-back" stage sab is shelf ke bina kuch nahi hain.

3. Memory aur addresses

Figure 3 — yeh padho: har chhota kaala box ek byte-mailbox hai jiska apna address number neeche hai. Laal outline chaar consecutive bytes ko ek instruction word mein group karta hai. Seekho: memory byte ke hisaab se numbered hoti hai, lekin hum cheezein chaar bytes ek saath lete hain.

Parent note mein do alag memories hain:

Instruction memory — run karte waqt read-only; tum use PC do, woh wahan ki instruction word wapas de deta hai.
Data memory — read aur write; sirf lw (load word) aur sw (store word) use karte hain.

Topic ko iske zaroorat kyun hai: MEM stage, MemRead, MemWrite, aur load/store instructions sab in mailboxes se baat karte hain.

4. Program Counter (PC)

Har cycle teen cheezein next PC ban sakti hain:

Seedha-ahead choice PC + 4 (line mein agla instruction chalao).
Branch choice — ek conditional redirect agar compare succeed kare (§8 mein Branch dekho).
Jump choice — ek unconditional redirect (§5 mein J-type dekho).

Adder (§7 dekho) naam ka ek chhota box PC + 4 compute karta hai jabki instruction ka baaki hissa execute hota hai. Agle bell par, chuna gaya value PC mein load hota hai.

Topic ko iske zaroorat kyun hai: poora Fetch stage hai "PC par instruction padho, phir agla PC decide karo."

5. Instruction fields: opcode, rs, rt, rd, immediate, funct, jump target

Ek instruction ek 32-bit word hai jo labelled slots mein kaati gayi hai. Tum inhe compute nahi karte — bas padh lete ho ki kaun se bits ka kya matlab hai. MIPS teen carvings use karta hai: R-type, I-type, aur J-type.

Definition J-type aur jump ke liye PC kaise update hota hai

Ek J-type instruction (j target) ek unconditional jump hai: yeh hamesha PC ko redirect karta hai, bina kisi compare ke. Iske 32 bits bas ek 6-bit opcode aur ek 26-bit jump-target field hain. Lekin ek full address 32 bits hota hai — missing bits kahan se aate hain? $JumpAddress = top 4 bits (PC + 4) [31 : 28] ∥ 26 + 2 = 28 bits (target ≪ 2)$ Ise teen moves mein padho: (1) 26-bit target words count karta hai, toh ise left 2 se shift karo 28-bit byte address banane ke liye (wahi "×4" trick jaise branches — §6); (2) top 4 bits PC+4 se bina badle borrow kiye jaate hain (symbol $∥$ ka matlab hai "bit-strings ko chipkao"); (3) woh assembled 32-bit value agle bell par seedha PC mein load hoti hai — koi adder nahi, koi Zero check nahi. Isliye ek jump Branch aur Zero ko bilkul ignore karta hai; PC mux mein uska apna alag raasta hai.

Figure 4 — yeh padho: teen strips ek hi 6-bit laal opcode slot share karte hain. Upar wala (R-type) rd+funct par khatam hota hai; beech wala (I-type) ek 16-bit immediate par; neeche wala (J-type) mein ek wide 26-bit jump target hai. Seekho: wahi 32 bits, teen alag carvings.

Topic ko iske zaroorat kyun hai: note mein har mux (§8 mein defined) isliye exist karta hai kyunki alag instruction types apne operands usi 32-bit word ke alag fields se lete hain — aur jump target woh field hai jo seedha PC ko feed karta hai.

6. Sign extension, zero extension, aur left shift

Immediate sirf 16 bits hai, lekin ALU 32-bit words par kaam karta hai. Hume ise 32 bits tak badhana hai — lekin kaise hum naye high bits bharte hain woh instruction par depend karta hai.

Topic ko iske zaroorat kyun hai: branch-target formula $(PC + 4) + (SignExt(imm) ≪ 2)$ sign-extension then shift use karta hai; jump apne 26-bit target par wahi "×4" shift use karta hai; aur andi/ori ko zero-extension path chahiye.

7. Adders, ALU, aur "delay" ka matlab

ALU ek extra 1-bit signal bhi emit karta hai:

8. Multiplexer (mux) aur uske select signals

Figure 5 — yeh padho: do kaalee arrows laal mux mein baayein taraf se enter karti hain; sirf ek daayein taraf nikalti hai. Neeche se upar aane wali arrow select control wire hai jo decide karti hai kaun sa input jitega. Seekho: mux ek controllable one-of-many switch hai, koi calculator nahi.

Definition Named control signals

Har ek control wire hai jo control unit opcode se set karta hai. Inhe ab milte hain taaki parent note smoothly padha ja sake:

ALUSrc — ALU ki second input select karta hai: register rt value (0) vs. extended immediate (1). R-type register chahta hai; lw/sw/addi immediate chahte hain.
MemToReg — select karta hai ki register mein kya write-back hoga: ALU result (0) vs. data-memory output (1). add ALU result chahta hai; lw memory data chahta hai.
RegDst — select karta hai ki kaun sa field destination register name karta hai: rt (0) vs. rd (1). I-type destination rt hai; R-type destination rd hai.
Branch — ek standalone control line jo sirf branch instructions (beq) ke liye 1 hoti hai. Akele yeh PC redirect nahi karta; yeh bas kehta hai "yeh ek branch hai, toh agar compare succeed kare, target lo." PC redirect karne ke liye ise ALU ke Zero output ke saath AND kiya jaata hai, PCSrc banane ke liye.
PCSrc — next PC select karta hai: PC + 4 (0) vs. branch target (1). Yeh ek raw control bit nahi hai; yeh Branch AND Zero ke roop mein compute hota hai, toh ek branch tabhi redirect karta hai jab woh taken ho. (Ek unconditional jump ka PC mein apna alag raasta hai — §5 dekho.)
ALUOp — koi mux select nahi balki woh chhota code hai jo ALU ko batata hai ki kaun sa operation perform karna hai (lw/sw ke liye add, beq ke liye subtract, ya R-type ke liye "look at funct").

Topic ko iske zaroorat kyun hai: yeh paanch naam parent note ki control table mein har jagah aate hain; yahan inhe ek baar mux idea se define kiya gaya hai.

Neeche diye prerequisite map ko kaise padhen

Yeh diagram ek dependency ladder hai: har arrow matlab hai "tumhe tail par box samajhna chahiye pehle head par box sense banana shuru ho." Arrows jo direction mein point karte hain usi direction mein follow karo. Baayein/upar sab raw material hai; saare raaste ek hi node "Single-cycle datapath" mein funnel hote hain neeche — wahi note hai jiske liye tum prepare kar rahe ho. Agar kisi box mein incoming arrow kisi aisi cheez ki taraf se point kare jo tum abhi explain nahi kar sakte, wapas jao aur woh pehla section phir padho.

9. Clock period inequality

Topic ko iske zaroorat kyun hai: poora "single-cycle slow hai" argument, Performance equation, aur Pipelining ki motivation is ek inequality par tikti hai.

Prerequisite map

(Reading guide aur diagram bilkul §9 se upar hain — wapas refer karo dekho ki har foundation topic ko kaise feed karta hai.)

Equipment checklist

Khud ko test karo — parent note padhne se pehle tumhe har ek ka jawab dena aana chahiye.

Kaun sa bit least-significant hai, aur bit k ki place value kya hai?

Bit 0 least-significant hai (ones place); bit k

2^{k}

carry karta hai.

32 registers mein se ek ko name karne ke liye kitne bits chahiye, aur kyun?

5 bits, kyunki

2^{5} = 32

MIPS register

0

mein kya khaas hai?

Yeh hard-wired to 0 hai: reads hamesha 0 return karte hain aur writes ignore hoti hain.

Ek MIPS instruction kitne bytes ki hoti hai, aur toh agla instruction ka address kya hai?

4 bytes; agla address = PC + 4.

lw/sw kaun se addresses touch kar sakte hain, aur us property ko kya kehte hain?

Sirf 4 ke multiples (bottom two bits zero); ise word-aligned kehte hain.

5-bit register number leta hai aur us register ki 32-bit value return karta hai.

Clock edge par, sirf jab RegWrite = 1 ho (aur kabhi

0

mein nahi).

MIPS kaunse teen field-carvings use karta hai, aur woh kaise differ karte hain?

R-type (rs rt rd shamt funct), I-type (rs rt 16-bit immediate), J-type (26-bit jump target).

J-type jump ke liye PC kaise set hota hai?

PC+4 ke top 4 bits, 26-bit target ko left 2 shift karke glued — seedha PC mein load.

Sign extension kya hai aur kaun sa bit copy hota hai?

16-bit value ko 32 bits tak badhana uske top (sign) bit ko saare naye high bits mein copy karke.

Hum sign-extend ki bajaye zero-extend kab karte hain, aur kyun?

Logical immediates jaise andi/ori ke liye, kyunki unka immediate ek unsigned bit-mask hai.

Left shift by 2 number ke saath kya karta hai, aur kyun?

Use 4 se multiply karta hai, kyunki har left shift use double karta hai.

Branch immediate ke liye sahi order kya hai?

Pehle 32 bits tak sign-extend karo, phir left 2 shift karo.

ALU ka Zero output kya hai aur woh kab 1 hota hai?

Ek 1-bit wire jo 1 hoti hai exactly jab ALU result 0 ho (beq ke liye use hota hai).

Multiplexer kya hai aur use kaun control karta hai?

Ek selector jo kai input buses mein se ek ko output mein pass karta hai, ek select control wire ke zariye choose kiya jaata hai.

Branch control line kya hai, aur yeh PCSrc se kaise differ karta hai?

Branch sirf branch instructions ke liye 1 hota hai; PCSrc = Branch AND Zero actually PC redirect karta hai.

ALUSrc, MemToReg, aur RegDst har ek kya select karta hai?

ALU ki 2nd input (reg vs imm); write-back source (ALU vs memory); destination field (rt vs rd).

Ek box ki "delay" kya hoti hai?

Uski input change hone ke baad output ke settle hone ka worst-case time.

Single-cycle mein PC+4 ke liye alag adder kyun chahiye?

ALU usi cycle mein instruction ke apne arithmetic mein busy hota hai aur time-share nahi ho sakta.

Clock period kaun si inequality set karta hai?

T_{c l k} \geq

saare instruction paths par sabse bada total box-delay.