Single-cycle datapath design — Hinglish notes

5.2.1 · Hardware › Processor Datapath & Pipelining

WHAT hai single-cycle datapath?

Building blocks (classic MIPS-style RISC example use karte hue):

Block	WHAT karta hai
PC (Program Counter)	Current instruction ka address hold karta hai
Instruction Memory	Address PC par instruction read karta hai
Register File	Register operands ke liye 2 read ports + 1 write port
ALU	Arithmetic/logic + address computation + branch compare
Data Memory	Memory ka load/store access
Sign-extender	16-bit immediate ko 32 bits mein convert karta hai
Muxes	Alternative data sources mein se select karta hai
Adders	`PC+4` aur branch target compute karte hain

HOW data flow hota hai (5 conceptual stages, sab ek hi cycle mein)

Bhaले yeh single-cycle hai, phir bhi hum un logical stages ko naam de sakte hain jinse signal guzarta hai:

Fetch (IF): Instruction ← InstrMem[PC]; PC+4 compute karo.
Decode / Register read (ID): rs, rt read karo; immediate sign-extend karo; control generate karo.
Execute (EX): ALU arithmetic karta hai ya address / branch decision compute karta hai.
Memory (MEM): Load Data Mem se read karta hai; store usmein write karta hai. (R-type yahan kuch nahi karta.)
Write-back (WB): Result register file mein likha jaata hai.

WHY har mux ki zaroorat hai? (Design ka dil)

ALUSrc mux — R-type chahta hai ki ALU ka 2nd input ek register (rt) ho; load/store/immediate sign-extended immediate chahte hain. Disagreement hai → mux.
MemToReg mux — R-type ALU result write-back karta hai; load memory data write-back karta hai. Disagreement → mux.
RegDst mux — R-type ka destination field rd hai (bits 15–11); I-type ka destination rt hai (bits 20–16). Disagreement → mux.
PCSrc mux — normally next PC = PC+4; ek taken branch branch target chahta hai. Disagreement → mux, Branch AND Zero se control hota hai.

Control signals — inhe derive karo, memorize mat karo

Opcode ek truth table mein ek row select karta hai. Har signal ke liye poocho: "IS instruction ko kya chahiye?"

Signal	R-type (`add`)	`lw`	`sw`	`beq`
RegWrite	1	1	0	0
ALUSrc (imm use karo?)	0	1	1	0
MemRead	0	1	0	0
MemWrite	0	0	1	0
MemToReg	0	1	X	X
RegDst (=rd?)	1	0	X	X
Branch	0	0	0	1
ALUOp	funct	add	add	sub

WHY single-cycle slow hai: clock period

Forecast-then-Verify

Recall Forecast: agar hum ek single-cycle CPU mein ek

mul instruction add karein jiska ALU stage 200 ps ki jagah 500 ps leta hai, toh kya hoga? Verify: Nayi lw-style critical path nahi badalti, lekin mul path ban jaata hai $200 + 100 + 500 + 100 = 900$ ps. Kyunki clock = sabhi instructions ka max, $T_{c l k}$ 800 se badhkar 900 ps ho jaata hai HAR instruction ke liye. Ek slow instruction sab ko penalize karti hai — yahi single-cycle ka fundamental flaw hai.

Common mistakes

Active-recall flashcards

#flashcards/hardware

Single-cycle datapath: ek instruction mein kitne cycles lagte hain?

Exactly ek (CPI = 1).

Single-cycle clock period kya determine karta hai?

Sabse slow instruction ke longest path ki delay (sabhi instructions ka max).

MIPS single-cycle mein usually critical path wali instruction kaun si hai, aur kyun?

lw, kyunki yeh dono memories samet paanch stages se guzarti hai.

ALUSrc mux kiske beech choose karta hai?

ALU ka second operand: register rt value vs. sign-extended immediate.

MemToReg mux kiske beech choose karta hai?

RegDst mux kiske beech choose karta hai?

Destination register field: rd (R-type) vs. rt (I-type).

Branch target address ka formula?

(PC+4) + (SignExt(imm) << 2).

Branch immediate ko 2 se left shift kyun karte hain?

Offset instruction words mein hota hai; ×4 byte address mein convert karta hai.

Taken branch ke liye PCSrc mux ko kaun control karta hai?

Branch signal AND ALU Zero output.

sw ke liye RegWrite = 0 kyun set karte hain?

Store register file ke liye koi result produce nahi karta; likhne se register corrupt ho jaata.

Single-cycle mein ek fast add slow kyun hoti hai?

Sabhi instructions ek hi lamba clock period share karti hain jo sabse slow ke hisaab se set hota hai.

PC+4 aur branch target ko alag adders kyun chahiye (ALU nahi)?

Ek cycle mein ALU apni khud ki arithmetic mein busy hota hai; ek cycle ke andar time-share nahi ho sakta.

Recall Feynman: ek 12-saal ke bachche ko samjhao

Socho ek factory jahan ek toy ko 5 machines se guzarna hota hai ek ke baad ek: unpack → instructions padho → banao → paint karo → wrap karo. Ek single-cycle factory mein, tum demand karte ho ki EK poora toy ghanti ki EK ring mein finish ho. Toh ghanti utni hi tez baj sakti hai jitna woh toy le leta hai jise paanchon machines chahiye aur sabse slow paint. Koi aisa toy jo painting skip karta hai woh bhi usi slow ghanti ka intezaar karta hai. Ise banana simple hai (har machine ke paas apne tools hain, koi share nahi karta) lekin wasteful hai — sab slowpoke ka intezaar karte hain.

Connections

Pipelining — stages ko overlap karke single-cycle ka wasted time fix karta hai.
Multi-cycle datapath — cycles ke across ek ALU reuse karta hai; alag tradeoff.
Control unit design — opcode → control-signal truth table kaise banti hai.
ALU design — critical path par woh block.
Performance equation — CPI × clock period × instruction count.
Memory hierarchy — instruction/data memory access times period dominate karti hain.