The four inter-stage registers are named IF/ID, ID/EX, EX/MEM, MEM/WB. They carry data (operands, immediate, ALU result) and control signals (RegWrite, MemRead, MemWrite, ...) forward, because control decisions made in ID must reach WB four cycles later.
Imagine washing dishes with 5 steps: scrape, wash, rinse, dry, stack. If one kid does all 5 for a plate before touching the next plate, four steps are always doing nothing. Instead, put 5 kids in a line — as soon as the "scrape" kid finishes plate 1 and passes it on, they grab plate 2. Now a clean plate pops out at the end every few seconds even though each plate still takes 5 steps to travel the line. The little trays between kids that hold the half-done plate are the "pipeline registers." That's exactly how a CPU pipelines instructions.
What are the five classic pipeline stages in order?
IF (fetch), ID (decode/register read), EX (execute/address calc), MEM (memory access), WB (write back).
In which stage are source registers read, and in which are results written?
Read in ID; written in WB.
Why must the clock period equal the slowest stage delay plus latch overhead?
All stages share one clock; the pipeline advances every cycle so it is paced by its slowest stage, and each stage must latch its result (delay d). Tclk=max(ti)+d.
How many cycles to run N instructions through a k-stage pipeline (no stalls)?
k+(N−1) — k to fill, then one completes each subsequent cycle.
What is the ideal speedup limit of a k-stage pipeline as N→∞?
k× (throughput bounded by number of stages).
Does pipelining reduce the latency of a single instruction?
No — single-instruction latency slightly increases; it improves throughput (instructions per second).
What do pipeline registers (IF/ID, ID/EX, EX/MEM, MEM/WB) carry?
Data (operands, immediate, ALU result) AND control signals forward to the correct stage/cycle.
Which stages does a store (sw) actually use for its purpose?
IF, ID (read base+data), EX (address = base+offset), MEM (write); no WB.
Why do add-type instructions still pass through MEM and WB even though MEM is idle?
To keep all instructions the same 5-stage shape, so control is uniform and one instruction can finish every cycle.
Socho ek instruction ko complete karne ke liye 5 chhote kaam karne padte hain: instruction fetch karna (IF), decode + register padhna (ID), ALU se calculation (EX), memory access (MEM), aur result wapas register me likhna (WB). Agar hum ek instruction ke saare 5 kaam pehle poore karein phir agla shuru karein, to baaki hardware bekaar khadi rehti hai. Pipelining ek assembly line ki tarah kaam karti hai — jaise hi ek instruction IF se aage badhta hai, agla instruction turant IF me ghus jaata hai. Isse har clock cycle me ek naya instruction complete hone lagta hai.
Yaad rakho: pipelining ek single instruction ko tez nahi banati — uski latency thodi badh bhi jaati hai (5 stage + latch delay). Jo cheez sudhaarti hai wo hai throughput, matlab per second kitne instructions khatam ho rahe hain. Clock period slowest stage ke barabar hota hai (plus latch overhead d), kyunki saari stages ek hi clock pe chalti hain — line utni hi tez jitni sabse dheemi worker.
Formula bilkul simple hai: N instructions ke liye cycles =k+(N−1) — pehle k cycle pipe "bharne" me, phir har cycle me ek result. Bada N hone par speedup k (yahan 5) ke kareeb pahunch jaata hai, par practically hazards aur latch overhead ki wajah se thoda kam milta hai. Ye baat exam me bahut poochhi jaati hai, isliye latency vs throughput ka fark aur k+(N−1) formula pakka rat lo.
