Intuition The one core ideaA pipeline is an assembly line for instructions : the work of running one instruction is chopped into equal-time stages, and a new instruction enters every clock tick so several are in flight at once. Everything on this page is just the vocabulary you need to say that sentence precisely — clocks, stages, registers, and the little algebra of "how many ticks for N instructions".
Before you can read the parent note Classic 5-stage pipeline , you must own every word and symbol it throws at you. Below, each item gives plain meaning → the picture → why the topic needs it , ordered so each rests on the ones above.
An instruction is one small command the CPU knows how to obey — "add these two numbers", "load this word from memory", "store this word". Think of it as one line of a recipe .
Picture a to-do card. Each card says one tiny job. A program is a stack of these cards, and the CPU works through them one at a time — but (spoiler) it works on several partially at once. That overlap is the whole point of pipelining, so first we must agree that a program is a stream of these cards .
We need this because pipelining is about how many instructions we can push through per second — so "instruction" is our unit of counting.
Intuition Every instruction secretly has phasesEven one simple "add" is not instantaneous inside the CPU. The hardware must (1) go get the instruction, (2) figure out what it says, (3) actually do the math, (4) maybe touch memory, (5) save the answer. These are natural, ordered phases — you literally cannot do step 3 before step 1.
Look at the figure: the five coloured blocks are the phases in order. The arrows show the forced order — each block needs what the previous one produced. That forced order is why there are stages at all, and why they line up in a chain.
Definition The five stage names (learn the labels only — details live in the parent)
IF = Instruction Fetch: go get the card.ID = Instruction Decode: read the card and grab the numbers it needs.EX = Execute: the actual arithmetic.MEM = Memory: read or write data memory (some cards skip this).WB = Write Back: save the result.
You need these five names memorised because the parent note refers to them constantly; here we only fix the labels and order , not the internal wiring.
Definition Clock and clock cycleA clock is a signal that ticks on and off forever, like a metronome. One clock cycle is the time between two ticks. All the moving parts of the CPU take their step exactly on the tick , so everything marches together.
Imagine a square wave: up, down, up, down. The rising edge (the moment it jumps from low to high) is the "GO!" signal. On every GO!, each pipeline stage hands its half-done work to the next stage. Nothing moves between ticks — the tick is the heartbeat.
In the figure, the ↑ marks are rising edges. We need the clock because pipelining works only if all stages advance in lockstep — one shared drumbeat. See Clocking & Latch Overhead for what the tick physically costs.
T c l k T c l k duration of one clock cycle , measured in time (nanoseconds ns or picoseconds ps). 1 ns = 1000 ps
Intuition Why a symbol at all?We will multiply "number of ticks" by "seconds per tick" to get total time. So we need a name for "seconds per tick" — that name is T c l k
T c l k pace . A smaller T c l k
t i t i i i which stage: t 1 t 2 t 5
max i ( t i ) max i ( t i ) t 1 , … , t 5 largest one . The little i max says "as i
max , not the sum or average?
Every stage shares the same clock. The tick cannot end until even the slowest stage has finished, or that stage would hand over garbage. So the tick must be at least as long as the slowest stage — the max. Picture five workers who must all clap together: they can only clap as fast as the slowest worker can finish.
The bar chart shows five stage delays. The red dashed line sits at the tallest bar — that height is max i ( t i ) wasted slack (that stage sits idle waiting for the tick). This picture is why "unbalanced stages" hurt.
Definition Latch overheadd d capture its value on the tick. So the real tick length is:
T c l k = max i ( t i ) + d
We need d why infinite stages don't give infinite speedup — the topic's key limitation. More in Clocking & Latch Overhead .
Definition Pipeline registerA pipeline register is a bank of memory cells (flip-flops) sitting between two stages . On each tick it snapshots everything the later stages will need, so each stage works on the right instruction's data. The four are named IF/ID, ID/EX, EX/MEM, MEM/WB .
Intuition The picture — trays on a conveyorBetween each pair of workers on an assembly line there's a tray holding the half-built product. Worker 2 always looks in the tray behind them, never at worker 3's hands. Without trays, fast and slow workers would collide. The register file that stages read from and write to is a different thing — see Register File .
Because five stages run at once on five different instructions, without these trays the data of instruction A and instruction B would smear together. That is the mistake pipeline registers prevent.
Definition The counting symbols
N k k = 5
Intuition Deriving "cycles for N instructions" by watching the pipe fillWatch the first instruction. It must crawl through all k k moment it exits, the second instruction is right behind it and finishes on the very next tick, then the third, and so on. So after the first, each remaining N − 1 one more tick:
cycles = k + ( N − 1 )
The diagonal chart is the classic pipeline diagram: rows are instructions, columns are ticks. The staircase shows the fill (first result at column k see k + ( N − 1 )
Instruction = one command
Five sub-steps IF ID EX MEM WB
Pipeline registers hold between-stage data
cycles = k plus N minus 1
The map reads bottom-right: instructions become stages, the clock sets the pace, the max plus d T c l k Classic 5-stage pipeline .
Test yourself — you should be able to answer each before reading the parent note.
What is an instruction, and why do we count instructions here? One small CPU command (add/load/store); it is our unit for measuring throughput (instructions per second).
Name the five stages in order. IF (fetch), ID (decode/read), EX (execute), MEM (memory), WB (write back).
What is a clock cycle and what happens on its rising edge? The time between two ticks; on the rising edge every stage hands its half-done work to the next stage in lockstep.
What does T c l k The duration of one clock cycle, in ns or ps (1 ns = 1000 ps).
What does max i ( t i ) The largest stage delay; the tick must fit even the slowest stage since all stages share one clock.
What is the latch overhead d Small fixed time each cycle for a pipeline register to reliably capture its value; T c l k = max i ( t i ) + d
What is a pipeline register (a tray) for? To hold one instruction's between-stage data/control so stages running on different instructions don't smear together.
What do N k N k
How many cycles for N k k + ( N − 1 ) k
What does ideal speedup approach as N → ∞ k ( k − 1 ) k