5.2.3 · D5Processor Datapath & Pipelining
Question bank — Classic 5-stage pipeline (IF - ID - EX - MEM - WB)
Before we start, one word we lean on constantly: a stage is one segment of the assembly line (IF, ID, EX, MEM, WB), and a pipeline register is the little bank of flip-flops that freezes one instruction's half-done results between two stages so the neighbouring instruction's data can't leak in.
True or false — justify
TF — "Pipelining makes every individual instruction complete in less time."
False. A single instruction still walks all five stages, and now pays latch overhead at each boundary, so its latency rises slightly; what improves is throughput (instructions finished per second).
TF — "A 5-stage pipeline running one lone instruction is faster than a single-cycle datapath."
False. With no follow-on instructions there is nothing to overlap, so you pay 5 clock periods plus 4 latch delays to finish one instruction — slower than one combinational sweep. Pipelining only pays off on a stream.
TF — "If all five stages have equal delay, the ideal speedup is exactly 5."
Almost — it approaches 5 as the instruction count , but is strictly less for finite because of the fill cost, and less again once latch overhead is charged each cycle.
TF — "The clock period is set by the average stage delay."
False. Every stage gets one shared clock period, so the clock must fit the slowest stage: . The average is irrelevant; one slow stage paces the whole line.
TF — "Adding more pipeline stages always increases speedup."
False. Each new boundary adds latch overhead ; as stages shrink, becomes a large fraction of , and hazards multiply, so speedup saturates and can even fall. See Clocking & Latch Overhead.
TF — "Register operands are read in the EX stage because that's where they're used."
False. Operands are read in ID and results written in WB. EX only consumes the values already latched in ID/EX; the Register File is touched only in ID (read) and WB (write).
TF — "An add instruction skips the MEM stage entirely to save a cycle."
False. It still passes through MEM doing nothing — every instruction keeps the same 5-stage shape so control stays uniform and one instruction can still finish each cycle. Skipping would break the lock-step.
TF — "Pipeline registers only carry data like operands and ALU results."
False. They also carry control signals (RegWrite, MemRead, MemWrite, ...) forward, because a decision made in ID must arrive at MEM/WB several cycles later on the same instruction.
TF — "In steady state all five stages are always doing useful work."
False. Even hazard-free, stages like MEM for arithmetic ops or WB for stores are idle for that instruction; and during fill/drain some stages hold nothing. "Full" means one instruction per stage, not every stage doing real work.
Spot the error
Spot the flaw: "Since the pipeline finishes one instruction per cycle, N instructions take exactly N cycles."
It ignores the fill cost. The first result appears only at cycle , so total cycles are , not . The one-per-cycle rate starts after the pipe is full.
Spot the flaw: "We can drop the IF/ID register because IF and ID run in the same cycle anyway."
They run in the same cycle on different instructions. Without the latch, the instruction being fetched would corrupt the one being decoded — the register is exactly what keeps neighbours separate.
Spot the flaw: "A value written to a register in WB this cycle cannot possibly be read until next cycle."
The classic fix is to write the Register File in the first half of the cycle and read in the second half, so a WB-this-cycle value is readable by an ID-this-cycle instruction. Without that trick you'd need an extra stall.
Spot the flaw: "To make the pipeline faster, just lower the clock period below the slowest stage's delay."
Then the slowest stage's combinational logic can't settle before the latch samples it, capturing garbage. The clock is floored by ; you must shorten the slowest stage, not just the clock.
Spot the flaw: "Since a sw (store) computes no result, it can skip WB and free that slot for another instruction."
A store indeed has no WB write, but its slot cannot be handed to another instruction — the lock-step advance means each cycle each stage holds exactly one instruction. The store simply idles WB; nothing jumps the queue.
Spot the flaw: "Total combinational work is 750 ps, so pipelining gives a 5× speedup at one instruction per 150 ps."
The pipeline period is set by the slowest stage plus , not by dividing total work by 5. Unbalanced stages waste slack in fast stages, so throughput is one per , giving less than 5×.
Why questions
Why do we place a pipeline register between every pair of stages, not just one central buffer?
Because five different instructions occupy the five stages simultaneously, and each stage needs its own instruction's partial results. Every boundary must independently freeze and forward its slice of state.
Why does the speedup cap at (the number of stages) and never exceed it?
You can at best overlap instructions at once, so throughput improves by at most a factor of . The fill cost only ever reduces this ideal, never beats it.
Why must control signals decided in ID travel all the way down the pipeline registers?
Because the actions they control (memory access, register write) happen cycles later in MEM and WB, but the decision can only be made once the opcode is decoded in ID — so the signal rides along with its instruction.
Why is an unbalanced pipeline (stages of unequal delay) wasteful?
The clock stretches to the slowest stage, so every faster stage sits idle for the leftover slack each cycle. Balancing stage delays is what lets shrink toward the ideal.
Why does per-instruction latency get worse under pipelining even though throughput improves?
Each of the boundaries adds latch delay , so one instruction's trip is instead of a single combinational sweep of the summed work. See Single-cycle vs Multicycle Datapath.
Why keep idle MEM/WB slots for arithmetic instructions instead of a shorter custom path?
Uniform 5-stage shape keeps control logic simple and preserves the one-finish-per-cycle rhythm; variable-length paths would collide and need complex arbitration.
Edge cases
Edge case — what is the speedup when (a single instruction)?
: no speedup at all, and in real hardware slightly worse than single-cycle because of the added latch overhead. Overlap needs a stream.
Edge case — what does the pipeline do during the first cycles?
It is filling: only the earliest stages hold real instructions and no result has emerged yet. The first completion happens at cycle , which is why total cycles are .
Edge case — what happens in the last cycles after the final instruction is fetched?
The pipe drains: later stages still process the tail of the stream while the front stages sit empty. These drain cycles are the mirror image of the fill cost.
Edge case — if latch overhead grows until it dominates , what limits speedup?
Speedup collapses toward 1, since almost the entire clock period is spent latching rather than computing. This is why you can't split into arbitrarily many tiny stages — see Clocking & Latch Overhead.
Edge case — a nop (no-operation) instruction: does it still consume all five stages?
Yes. It flows through IF/ID/EX/MEM/WB like any instruction, simply asserting no writes. This is exactly how a stall/bubble is injected — a disguised nop occupying a slot. See Pipeline Hazards (structural, data, control).
Edge case — with only one stage () does "pipelining" mean anything?
No. for all : a single stage is just the single-cycle datapath, with nothing to overlap and no inter-stage register to add.
Edge case — an instruction that neither reads memory nor writes a register (e.g. a plain store to nowhere / a nop store): which stages carry real work?
Only IF, ID, and EX do anything meaningful; MEM and WB idle. Yet the instruction still occupies those two stages to preserve lock-step timing.
Recall One-line survival summary
Reads in ID, writes in WB; clock = ==slowest stage + ; N instructions take cycles; pipelining boosts throughput, not single-instruction latency; speedup caps at ==. Trap-proof if you keep these five straight.