5.2.3 · D1Classic 5-stage pipeline (IF - ID - EX - MEM - WB)
Ek pipeline ek assembly line hai instructions ke liye : ek instruction chalane ka kaam equal-time stages mein kaata jaata hai, aur har clock tick pe ek naya instruction enter karta hai — toh kai ek saath "in flight" hote hain. Is page ka saara content bas woh vocabulary hai jo tumhe yeh sentence precisely kehne ke liye chahiye — clocks, stages, registers, aur "N instructions ke liye kitne ticks" ka chhota sa algebra.
Parent note Classic 5-stage pipeline padhne se pehle, tumhe uske har word aur symbol ka maloom hona chahiye. Neeche, har item plain meaning → picture → topic ko yeh kyun chahiye deta hai, is order mein ki har cheez upar wali cheez pe tiki ho.
Ek instruction ek chhota sa command hai jo CPU maanna jaanta hai — "yeh do numbers add karo", "memory se yeh word load karo", "yeh word store karo". Ise recipe ki ek line samjho.
Ek to-do card socho. Har card kehta hai ek chhota sa kaam. Ek program aise cards ki stack hai, aur CPU unhe ek-ek karke karta hai — lekin (spoiler) woh kai ko ek saath partially karta hai. Yahi overlap pipelining ka poora point hai, toh pehle hum agree karte hain ki ek program aise cards ki stream hai.
Humein yeh isliye chahiye kyunki pipelining is baare mein hai ki hum per second kitne instructions push kar sakte hain — toh "instruction" hamaari counting ki unit hai.
Intuition Har instruction ke andar secretly phases hote hainEk simple "add" bhi CPU ke andar instantaneous nahi hai. Hardware ko (1) instruction laana padta hai, (2) samajhna padta hai kya keh raha hai, (3) actually math karna padta hai, (4) shayad memory touch karni padti hai, (5) answer save karna padta hai. Yeh natural, ordered phases hain — tum literally step 3 step 1 se pehle nahi kar sakte.
Figure dekho: paanch coloured blocks ordered phases hain. Arrows forced order dikhate hain — har block ko pichle wale ki production chahiye. Yahi forced order hai kyun stages hote hain, aur kyun woh ek chain mein line up hote hain.
Definition Paanch stage names (sirf labels seekho — details parent mein hain)
IF = Instruction Fetch: card laao.ID = Instruction Decode: card padho aur usse jo numbers chahiye woh pakdo.EX = Execute: actual arithmetic.MEM = Memory: data memory read ya write karo (kuch cards yeh skip karte hain).WB = Write Back: result save karo.
Tumhe yeh paanch names yaad hone chahiye kyunki parent note inhe baar baar refer karta hai; yahan hum sirf labels aur order fix karte hain, internal wiring nahi.
Definition Clock aur clock cycleEk clock ek signal hai jo hamesha on aur off hota rehta hai, jaise ek metronome. Ek clock cycle do ticks ke beech ka time hai. CPU ke saare moving parts apna step exactly tick pe lete hain, toh sab milkar march karte hain.
Ek square wave socho: upar, neeche, upar, neeche. Rising edge (woh moment jab yeh low se high jaata hai) "GO!" signal hai. Har GO! pe, har pipeline stage apna adha-kiya kaam agले stage ko de deta hai. Ticks ke beech mein kuch nahi hilta — tick hi heartbeat hai.
Figure mein, ↑ marks rising edges hain. Humein clock isliye chahiye kyunki pipelining tabhi kaam karti hai jab saari stages lockstep mein aage badhein — ek shared drumbeat. Dekhte hain Clocking & Latch Overhead tick physically kya cost karta hai.
T c l k T c l k ek clock cycle ki duration hai, time mein measure ki hui (nanoseconds ns ya picoseconds ps). 1 ns = 1000 ps
Hum "number of ticks" ko "seconds per tick" se multiply karenge total time nikalne ke liye. Toh humein "seconds per tick" ka ek naam chahiye — woh naam hai T c l k
T c l k pace hai. Chhota T c l k
t i t i i i kaunsa stage label karta hai: t 1 t 2 t 5
max i ( t i ) max i ( t i ) t 1 , … , t 5 sabse bada chuno. max ke neeche i i
Max kyun, sum ya average kyun nahi?
Har stage ek hi clock share karta hai. Tick tab tak khatam nahi ho sakta jab tak sabse slow stage bhi finish na kar le, warna woh stage garbage hand over kar dega. Toh tick kam se kam itni lambi honi chahiye jitni sabse slow stage — yani max. Paanch workers socho jo sab milkar clap karenge: woh sirf utni fast clap kar sakte hain jitni fastest the slowest worker finish kar sake.
Bar chart paanch stage delays dikhata hai. Red dashed line sabse tall bar pe baithti hai — woh height max i ( t i ) wasted slack hai (woh stage idle baith ke tick ka wait karta hai). Yahi picture hai kyun "unbalanced stages" nuksan deti hain.
Definition Latch overheadd d capture karne ke liye ek moment chahiye. Toh real tick length hai:
T c l k = max i ( t i ) + d
Humein d wajah hai ki infinite stages infinite speedup nahi dete — topic ki key limitation. Zyada jaankari Clocking & Latch Overhead mein.
Definition Pipeline registerEk pipeline register memory cells (flip-flops) ka ek bank hai jo do stages ke beech baitha hai. Har tick pe yeh sab kuch snapshot karta hai jo baad ki stages ko chahiye hoga, taki har stage sahi instruction ka data dekhe. Chaar hain jinke naam hain IF/ID, ID/EX, EX/MEM, MEM/WB .
Intuition Picture — conveyor pe traysAssembly line pe har do workers ke beech ek tray hoti hai jo adha-bana product hold karti hai. Worker 2 hamesha apne peeche ki tray mein dekhta hai, worker 3 ke haathon mein nahi. Trays ke bina, fast aur slow workers collide kar dete. Woh register file jisse stages read aur write karti hain woh alag cheez hai — dekhte hain Register File .
Kyunki paanch stages ek saath paanch alag instructions pe chalti hain, inke bina instruction A aur instruction B ka data ek saath mix ho jaata. Yahi galati pipeline registers rokti hain.
Definition Counting symbols
N k k = 5
Intuition "N instructions ke liye cycles" derive karna — pipe fill hote dekh kePehle instruction ko dekho. Use saare k k jaise hi woh exit karta hai, doosra instruction theek uske peeche hai aur agле tick pe finish ho jaata hai, phir teesra, aur aise aage. Toh pehle ke baad, baaki N − 1 ek aur tick layta hai:
cycles = k + ( N − 1 )
Diagonal chart classic pipeline diagram hai: rows instructions hain, columns ticks hain. Staircase fill dikhata hai (pehla result column k k + ( N − 1 ) dekh lete ho.
Instruction = one command
Five sub-steps IF ID EX MEM WB
Pipeline registers hold between-stage data
cycles = k plus N minus 1
Map bottom-right padhta hai: instructions stages ban jaate hain, clock pace set karta hai, max plus d T c l k Classic 5-stage pipeline ko feed karte hain.
Khud test karo — parent note padhne se pehle tum har cheez ka jawab de sako.
Instruction kya hota hai, aur hum yahan instructions kyun count karte hain? Ek chhota CPU command (add/load/store); yeh throughput measure karne ki hamaari unit hai (instructions per second).
Paanch stages ke naam order mein batao. IF (fetch), ID (decode/read), EX (execute), MEM (memory), WB (write back).
Clock cycle kya hota hai aur uske rising edge pe kya hota hai? Do ticks ke beech ka time; rising edge pe har stage apna adha-kiya kaam lockstep mein agले stage ko de deta hai.
T c l k Ek clock cycle ki duration, ns ya ps mein (1 ns = 1000 ps).
max i ( t i ) Sabse bada stage delay; tick sabse slow stage ke saath bhi fit hona chahiye kyunki saari stages ek clock share karti hain.
Latch overhead d Har cycle mein ek chhota fixed time jo pipeline register ko apni value reliably capture karne mein lagta hai; T c l k = max i ( t i ) + d
Pipeline register (tray) kis kaam aata hai? Ek instruction ka between-stage data/control hold karne ke liye taki alag instructions pe chalti stages ka data mix na ho.
N k N k
k N k + ( N − 1 ) k
Ideal speedup N → ∞ k ( k − 1 ) k