Chaar inter-stage registers ko IF/ID, ID/EX, EX/MEM, MEM/WB naam diya gaya hai. Yeh data (operands, immediate, ALU result) aur control signals (RegWrite, MemRead, MemWrite, ...) forward carry karte hain, kyunki ID mein liye gaye control decisions ko WB tak pahunchna hota hai chaar cycles baad.
Recall Feynman: ek 12-saal ke bache ko explain karo
Socho bartan dhone ke 5 steps hain: khaana saaf karo, dhoo, rinse karo, sukhaao, stack karo. Agar ek baccha ek plate ke liye saare 5 steps kare agali plate uthane se pehle, toh chaar steps hamesha kuch nahi karte. Iske bajaye, 5 bachche line mein khade karo — jaise hi "scrape" wala baccha plate 1 finish karke age bhejta hai, woh plate 2 uthata hai. Ab har kuch seconds mein ek clean plate akhir mein nikalti hai chahe har plate 5 steps leti ho line traverse karne mein. Bachcho ke beech ke chhote trays jo half-done plate hold karte hain woh "pipeline registers" hain. Bilkul aise hi CPU instructions ko pipeline karta hai.
Classic pipeline ke paanch stages order mein kya hain?
IF (fetch), ID (decode/register read), EX (execute/address calc), MEM (memory access), WB (write back).
Source registers kaun se stage mein read hote hain, aur results kaun se stage mein write hote hain?
ID mein read hote hain; WB mein write hote hain.
Clock period sabse slow stage delay plus latch overhead ke barabar kyun honi chahiye?
Sab stages ek clock share karte hain; pipeline har cycle advance hoti hai toh apne sabse slow stage ki pace se chalti hai, aur har stage ko apna result latch karna hota hai (delay d). Tclk=max(ti)+d.
k-stage pipeline mein N instructions (no stalls) kitne cycles mein chalenge?
k+(N−1) — k fill karne mein, phir har subsequent cycle mein ek complete hoti hai.
k-stage pipeline ka ideal speedup limit kya hai jab N→∞?
k× (throughput stages ki number se bounded hai).
Kya pipelining ek single instruction ki latency reduce karta hai?
Nahi — single-instruction latency thodi badhti hai; yeh throughput (instructions per second) improve karta hai.
