Full custom vs standard cell design — Hinglish notes

4.2.3 · Hardware › VLSI Design

YEH distinction exist hi kyun karti hai?

Poora spectrum teen competing pressures ki wajah se exist karta hai:

Pressure	Kisme pull karta hai
Performance / area / power extreme honi chahiye	Full custom
Time-to-market short hona chahiye	Standard cell
Design cost (engineer-hours) kam honi chahiye	Standard cell

HAR methodology actually kya hoti hai

Standard cells ki key enabling constraint:

Figure — Full custom vs standard cell design

DONO ka comparison (exam table)

Attribute	Full Custom	Standard Cell
Transistors kaun draw karta hai	Insaan	Library (pre-made)
Placement & routing	Manual	Automated (P&R tool)
Design time / cost	Bahut zyada	Kam–moderate
Performance	Sabse zyada	Achhi
Area (density)	Sabse zyada	Moderate (rows/whitespace waste)
Flexibility	Total	Library tak limited
Error-prone?	Haan (manual)	Kam (verified cells)
Typical use	CPU datapaths, analog, RAM, I/O	Random logic, ASICs, control
NRE cost	Bahut zyada	Kam

Trade-off ko quantitatively derive karna (first principles se)

Hum sirf "full custom denser hai" yaad nahi karte. Aao ek simple model banate hain taaki hum reason kar sakein.

Forecast-then-Verify

Recall Aage padhne se pehle predict karo: kaun si methodology zyada

density deti hai, aur kaun si faster time-to-market? Ek modern SoC actually kaun sa use karta hai? Density winner: Full custom (hand-optimized packing). Time-to-market winner: Standard cell (automated P&R, verified library). Real SoC: ek hybrid — datapath/memory/analog ke liye custom, control/random logic ke liye standard cell.

Common mistakes (Steel-manned)

Flashcards

Full custom design kya define karta hai?

Har individual transistor aur interconnect ka manual layout, ek specific function ke liye haath se optimize kiya gaya.

Standard cell design kya define karta hai?

Ek semi-custom style jo pre-characterized, fixed-height logic cells ki library use karta hai, place-and-route tools dwara automatically assemble kiya jaata hai.

Standard cells ka fixed height kyun hona chahiye?

Taaki cells rows mein align ho sakein jahan abutting power/ground rails hon, millions of gates ki automated placement & routing enable ho sake.

Kaun si methodology sabse zyada density aur performance deti hai?

Full custom.

Kaun si methodology sabse kam time-to-market aur lowest design cost deti hai?

Standard cell.

Design time par dono ke beech break-even transistor count kya hai?

N^{*} = L / (t_{c} - t_{s})

, jahan

L

=library cost,

t_{c}

t_{s}

=per-transistor custom/stdcell effort.

Same logic ke liye standard-cell area kyun badi hoti hai?

Routing channels/whitespace aur generically-sized cells se kam density; area

\propto 1/ density

Ek real SoC mein full custom typically kahan use hota hai?

Datapaths/ALUs, SRAM/memory bit-cells, analog blocks, PLLs, high-speed I/O.

Standard cell typically kahan use hota hai?

Random/control logic aur general ASIC glue logic.

SRAM 6T cell ke liye effort ke bawajood full custom worth it kyun hai?

One-time optimization millions of replicated copies par amortize ho jaata hai, har area/power saving ko multiply karta hai.

Gate array standard cell se kaise alag hai?

Gate array transistors pre-fabricate karta hai aur sirf wiring/metal layers customize karta hai; standard cell saari layers customize karta hai.

Kya standard cells "real hardware layout nahi" hain?

Nahi — yeh real transistor layouts hain, sirf library ne ek baar draw kiye aur reuse hote hain.

Recall Feynman: 12-saal ke bacche ko explain karo

Socho tum LEGO se build kar rahe ho. Full custom matlab har brick khud clay se sculpt karna — perfect shape ban sakta hai, lekin bahut time lagta hai. Standard cell matlab ready-made LEGO bricks ka box use karna jinka height same hota hai taaki woh jaldi snap ho sakein. Ready bricks jaldi hote hain aur rarely toote hote hain, lekin thoda sa haath se banaye jitne perfectly fit nahi hote. Smart builders sirf kuch khaas pieces haath se banate hain (jo parts mein sachchi perfection chahiye hoti hai) aur baaki sab ke liye ready bricks use karte hain.

Connections

Semi-custom design — standard cell + gate array dono yahan aate hain
Gate array design — sirf metal layers customize karta hai
Place and route (P&R) — woh tool flow jis par standard cells depend karti hain
Standard cell library characterization — cells ko timing/power models kaise milte hain
ASIC design flow — RTL → synthesis → P&R standard cells use karta hai
SRAM design — classic full-custom bit-cell
Datapath design — bit-sliced custom layout
Design productivity gap — "automate kyun karein" ka driver
Non-recurring engineering (NRE) cost — economic lever