Parasitic extraction (RC) — Hardware notes

WHY do parasitics exist at all?

WHY resistance? A wire of length $L$ , cross-sectional area $A=W\cdot t$ (width × thickness), made of material with resistivity $\rho$ , cannot conduct perfectly. Electrons scatter → finite $R$ .

WHY capacitance? Any two conductors separated by a dielectric store charge when at different voltages. A signal wire has neighbors: the substrate below, wires above/below/beside it. Each pairing = a capacitor.

WHY do we care? Interconnect RC dominates delay in modern nodes. Gate delay shrinks with scaling, but wires get thinner (↑R) and closer (↑C), so wire delay $\approx RC$ often exceeds gate delay. Miss it → chip fails timing → tape-out disaster.

HOW to derive wire Resistance from first principles

Start from Ohm's microscopic law. Resistance of a uniform block:

$R = \rho \frac{L}{A} = \rho \frac{L}{W\,t}$

Why this form? Longer wire = more scattering = more $R$ (∝ $L$ ). Fatter cross-section = more parallel paths = less $R$ (∝ $1/A$ ).

Since a given metal layer has fixed thickness $t$ , group the constants:

$R = \underbrace{\frac{\rho}{t}}_{\text{fixed per layer}} \cdot \frac{L}{W} = R_{\square}\cdot \frac{L}{W}$

Why "squares"? If $L=W$ , the shape is one square and $R=R_\square$ . Doubling both $L$ and $W$ keeps $R$ unchanged — resistance depends only on the aspect ratio, not absolute size (in-plane).

HOW to derive wire Capacitance

The simplest model is the parallel-plate capacitor between the wire (area $A = W\cdot L$ ) and ground plane, separated by oxide of thickness $h$ , permittivity $\varepsilon = \varepsilon_r\varepsilon_0$ :

$C_{\text{area}} = \varepsilon \frac{A}{h} = \varepsilon \frac{W L}{h}$

Why? Charge $Q=CV$ ; field between plates $E=V/h$ ; $Q=\varepsilon E A/...$ → the standard $C=\varepsilon A/d$ .

But a real wire is a thin rectangular bar, not an infinite plate. Field lines bulge out the sides → fringing capacitance. And it couples sideways to neighbors → coupling capacitance.

Miller effect (WHY coupling is worse than it looks): if a neighbor (aggressor) switches opposite to the victim, the effective coupling cap is doubled ( $C_{\text{eff}}=2C_c$ ) because the voltage across it swings twice as much. If it switches the same way, $C_{\text{eff}}\to 0$ .

HOW extraction represents a long wire: the RC ladder

A wire isn't a lumped R then a lumped C — R and C are distributed along its length. Extraction tools break the wire into segments, each a small $r,c$ , forming an RC ladder.

The Elmore delay gives the dominant delay of such a ladder. For a wire of length $L$ with per-unit resistance $r$ and capacitance $c$ , split into $N$ segments each carrying $c$ at the far end of resistance summing up:

$t_{ED} = \sum_i R_{i\to\text{source}}\,C_i$

For a uniform distributed line:

$t_{ED} = \sum_{k=1}^{N}\left(k\,\frac{rL}{N}\right)\left(\frac{cL}{N}\right) = \frac{rc L^2}{N^2}\sum_{k=1}^{N}k = \frac{rcL^2}{N^2}\cdot\frac{N(N+1)}{2}\xrightarrow{N\to\infty}\frac{rcL^2}{2}$

Extraction flow (WHAT the tool actually does)

Read layout (GDSII) + technology file (per-layer $\rho$ , $t$ , $\varepsilon$ , spacings).
Recognize geometry, count squares → compute R per net segment.
Compute area + fringe + coupling C using field solvers or pattern-matched formulas.
Emit a SPEF/DSPF file (Standard Parasitic Exchange Format) = the RC netlist.
Feed to STA (static timing analysis) and SPICE.

Two flavors:

Rule-based / pattern-matching extraction: fast, uses precomputed lookup tables. Good for signoff of billions of nets.
Field-solver extraction: solves Laplace's equation numerically. Accurate but slow; used for critical nets.

Worked Examples

Worked example Example 2 — Parallel-plate capacitance

$W=0.2\,\mu m$ , $L=20\,\mu m$ , oxide $h=0.4\,\mu m$ , $\varepsilon_r=3.9$ , $\varepsilon_0=8.85\times10^{-12}$ F/m. Step 1 — Area $A = WL = 0.2\times20 = 4\,\mu m^2 = 4\times10^{-12}\,m^2$ . Step 2 — $C = \varepsilon_r\varepsilon_0 A/h = 3.9\times8.85\text{e-}12\times \dfrac{4\text{e-}12}{0.4\text{e-}6}$ . Why divide by $h$ ? Closer plates → stronger field per volt → more stored charge. $= 3.9\times8.85\text{e-}12\times1\text{e-}5 \approx 3.45\times10^{-16}$ F $= 0.345$ fF.

Common Mistakes (Steel-manned)

Flashcards

What are the two dominant interconnect parasitics extracted in VLSI?

Resistance (R) and Capacitance (C) — L is usually ignored except for high-freq/global clock nets.

Define sheet resistance

R_\square

R_\square=\rho/t

, resistance of one unit square of a layer, in

\Omega/\square

; total

R=R_\square\cdot L/W

Why is wire resistance expressed in "squares"?

Because

R=\rho L/(Wt)=R_\square(L/W)

depends only on the aspect ratio

L/W

, not absolute size.

Give the parallel-plate capacitance formula and why it holds.

C=\varepsilon A/h

; closer/larger plates store more charge per volt due to stronger uniform field

E=V/h

What three components make up total wire capacitance?

Area (bottom-plate), fringe (edge fields), and coupling (to neighbor wires).

State the Elmore/distributed-wire delay and why the factor ½ appears.

t=\tfrac12 RC=\tfrac12 rcL^2

; ½ arises because charge near the source sees less resistance than charge at the far end.

How does interconnect RC delay scale with wire length?

Quadratically (

\propto L^2

), because both R and C grow linearly with L.

What is the Miller effect on coupling capacitance?

Effective

C_{couple}

2C_c

if aggressor switches opposite the victim,

0

if same direction,

C_c

if quiet.

What file format stores extracted parasitics?

SPEF (Standard Parasitic Exchange Format) / DSPF.

Rule-based vs field-solver extraction?

Rule-based uses precomputed lookup tables (fast, full-chip); field-solver solves Laplace's equation (accurate, critical nets).

Why are long global wires buffered/repeatered?

To break the

L^2

delay into smaller segments; N segments give delay

\propto (L/N)^2\times N = L^2/N

, so delay drops ~linearly with buffer count.

Coupling cap per length between two wires (spacing s, thickness t)?

C_c\approx \varepsilon\, t/s

per unit length — facing sidewalls act as small parallel plates.

Recall Feynman: explain to a 12-year-old

Imagine your wire is a garden hose carrying water (electric current). A perfect hose lets water through instantly. But real hoses have friction on the inside walls (that's resistance, R) — it slows the flow, more so for long thin hoses. Now imagine the hose is stretchy and surrounded by other hoses; pushing water in first has to inflate the walls a little before flow reaches the end (that's capacitance, C — storing charge). A long hose is both very draggy AND very stretchy, and the two effects multiply, so a hose twice as long is FOUR times slower to fill. "Parasitic extraction" is just carefully measuring how draggy and stretchy every hose in the chip is, so we can predict exactly when the water arrives.

Connections

Interconnect delay modeling — where extracted RC feeds delay calc.
Elmore delay — the math of RC ladders.
Static Timing Analysis (STA) — consumes the SPEF file.
Crosstalk and Signal Integrity — driven by coupling capacitance + Miller.
Repeater / Buffer insertion — the fix for $L^2$ delay.
Technology scaling (Dennard) — why wire parasitics dominate in modern nodes.
Sheet resistance · Parallel-plate capacitor — physics primitives.

Concept Map

Hinglish (regional understanding)

Intuition Hinglish mein samjho

Dekho, jab aap layout mein ek wire draw karte ho, toh aap sochte ho ki yeh perfect conductor hai — zero resistance, zero delay. Lekin reality mein har metal wire ek chhota resistor bhi hai (kyunki metal ki conductivity finite hai) aur ek capacitor bhi (kyunki wire ke aas-paas ground aur doosri wires hain, beech mein oxide hai). In "hidden" R aur C ko layout se nikalne ka process hi parasitic extraction kehlata hai. Yeh zaroori hai kyunki extract kiye bina aapka timing simulation silicon se match nahi karega.

Resistance nikalne ka funda simple hai: $R = R_\square \times (L/W)$ , jahan $R_\square = \rho/t$ ek layer ki fixed property hai. Aap bas "squares" gino — wire kitni baar apne width jitni length cover karti hai. Capacitance mein teen cheezein hain: area cap (neeche ground ke saath parallel-plate), fringe cap (edges se nikalne wale field lines), aur coupling cap (bagal ki wire ke saath). Advanced nodes mein wires patli aur paas-paas hoti hain, isliye coupling cap bahut bada ho jata hai — aur Miller effect isko double kar deta hai agar neighbor opposite direction mein switch kare.

Sabse important insight: wire ka delay $\frac{1}{2}RC$ hota hai, aur kyunki R aur C dono length ke saath badhte hain, delay $L^2$ ke proportional hai. Matlab wire double lambi karo toh delay char guna! Isiliye engineers lambi global wires ke beech mein buffers/repeaters lagate hain — length ko tukdon mein todkar quadratic delay ko control karte hain.

Exam aur real chip design dono mein yeh topic gold hai (80/20): squares se R, teen cap components, aur $\tfrac12 RC \propto L^2$ delay — bas yeh teen cheezein solid kar lo toh aadha VLSI interconnect samajh mein aa jayega.

Test yourself — VLSI Design

Connections