Parasitic extraction (RC) — Hinglish notes

4.2.10 · Hardware › VLSI Design

Parasitics exist kyun karte hain?

Resistance kyun? Length $L$ , cross-sectional area $A = W \cdot t$ (width × thickness), aur resistivity $ρ$ wale material ka wire perfectly conduct nahi kar sakta. Electrons scatter karte hain → finite $R$ .

Capacitance kyun? Koi bhi do conductors jo dielectric se separated hain, alag voltages par charge store karte hain. Ek signal wire ke neighbors hote hain: neeche substrate, uske upar/neeche/side mein wires. Har pairing = ek capacitor.

Hum care kyun karte hain? Modern nodes mein interconnect RC delay dominate karta hai. Gate delay scaling se chhota hota hai, lekin wires patalee hoti hain (↑R) aur paas aati hain (↑C), toh wire delay $\approx R C$ aksar gate delay se zyada hoti hai. Miss karo → chip timing fail kare → tape-out disaster.

Wire Resistance ko first principles se derive kaise karein

Ohm ke microscopic law se shuru karo. Ek uniform block ki resistance:

$R = ρ \frac{L}{A} = ρ \frac{L}{W t}$

Yeh form kyun? Lamba wire = zyada scattering = zyada $R$ (∝ $L$ ). Mota cross-section = zyada parallel paths = kam $R$ (∝ $1/ A$ ).

Kyunki ek given metal layer ki thickness $t$ fixed hoti hai, constants ko group karo:

$R = har layer ke liye fixed \frac{ρ}{t} \cdot \frac{L}{W} = R_{□} \cdot \frac{L}{W}$

"Squares" kyun? Agar $L = W$ ho, toh shape ek square hai aur $R = R_{□}$ . Dono $L$ aur $W$ ko double karne par $R$ same rehta hai — resistance sirf aspect ratio par depend karta hai, absolute size par nahi (in-plane).

Wire Capacitance derive kaise karein

Sabse simple model parallel-plate capacitor hai — wire (area $A = W \cdot L$ ) aur ground plane ke beech, oxide thickness $h$ , permittivity $ε = ε_{r} ε_{0}$ :

$C_{area} = ε \frac{A}{h} = ε \frac{W L}{h}$

Kyun? Charge $Q = C V$ ; plates ke beech field $E = V / h$ ; $Q = εE A /...$ → standard $C = ε A / d$ .

Lekin real wire ek thin rectangular bar hai, infinite plate nahi. Field lines sides se bahar bulge karti hain → fringing capacitance. Aur yeh sideways neighbors se couple karti hai → coupling capacitance.

Miller effect (coupling zyada bura kyun lagta hai):* agar ek neighbor (aggressor) victim ke opposite switch kare, toh effective coupling cap double ho jaati hai ( $C_{eff} = 2 C_{c}$ ) kyunki us par voltage swing do guna hoti hai. Agar woh same direction mein switch kare, toh $C_{eff} \to 0$ .

Extraction ek long wire ko kaise represent karta hai: RC ladder

Wire ek lumped R phir ek lumped C nahi hai — R aur C uski length mein distributed hote hain. Extraction tools wire ko segments mein todta hai, har ek chhota $r, c$ , jo ek RC ladder banata hai.

Elmore delay aise ladder ki dominant delay deta hai. Length $L$ ki wire ke liye, per-unit resistance $r$ aur capacitance $c$ ke saath, $N$ segments mein divide karke, har ek resistance ke far end par $c$ carry karta hai:

$t_{E D} = \sum_{i} R_{i \to source} C_{i}$

Ek uniform distributed line ke liye:

$t_{E D} = \sum_{k = 1}^{N} (k \frac{r L}{N}) (\frac{c L}{N}) = \frac{r c L ^{2}}{N ^{2}} \sum_{k = 1}^{N} k = \frac{r c L ^{2}}{N ^{2}} \cdot \frac{N ( N + 1 )}{2} N \to \infty \frac{r c L ^{2}}{2}$

Extraction flow (tool actually KAYA karta hai)

Layout (GDSII) + technology file (per-layer $ρ$ , $t$ , $ε$ , spacings) padho.
Geometry pehchano, squares gino → har net segment ka R compute karo.
Field solvers ya pattern-matched formulas se area + fringe + coupling C compute karo.
Ek SPEF/DSPF file (Standard Parasitic Exchange Format) emit karo = RC netlist.
STA (static timing analysis) aur SPICE ko feed karo.

Do flavors:

Rule-based / pattern-matching extraction: fast, precomputed lookup tables use karta hai. Billions of nets ke signoff ke liye achha.
Field-solver extraction: Laplace's equation numerically solve karta hai. Accurate lekin slow; critical nets ke liye use hota hai.

Worked Examples

Common Mistakes (Steel-manned)

Flashcards

VLSI mein extract kiye jaane waale do dominant interconnect parasitics kya hain?

Resistance (R) aur Capacitance (C) — L ko usually ignore kiya jaata hai sivaay high-freq/global clock nets ke.

Sheet resistance

R_{□}

define karo.

R_{□} = ρ / t

, ek layer ke ek unit square ki resistance,

Ω/ □

mein; total

R = R_{□} \cdot L / W

Wire resistance "squares" mein kyun express ki jaati hai?

Kyunki

R = ρ L / (W t) = R_{□} (L / W)

sirf aspect ratio

L / W

par depend karta hai, absolute size par nahi.

Parallel-plate capacitance formula kya hai aur yeh kyun hold karta hai?

C = ε A / h

; paas/bade plates per volt zyada charge store karte hain kyunki uniform field

E = V / h

zyada strong hoti hai.

Total wire capacitance ke teen components kya hain?

Area (bottom-plate), fringe (edge fields), aur coupling (neighbor wires ko).

Elmore/distributed-wire delay kya hai aur factor ½ kyun aata hai?

t = \frac{1}{2} R C = \frac{1}{2} r c L^{2}

; ½ isliye aata hai kyunki source ke paas ka charge far end ke charge se kam resistance dekhta hai.

Interconnect RC delay wire length ke saath kaise scale karta hai?

Quadratically (

\propto L^{2}

), kyunki R aur C dono L ke saath linearly badhte hain.

Coupling capacitance par Miller effect kya hota hai?

Effective

C_{co u pl e}

2 C_{c}

agar aggressor victim ke opposite switch kare,

0

agar same direction,

C_{c}

agar quiet ho.

Extracted parasitics kis file format mein store hote hain?

SPEF (Standard Parasitic Exchange Format) / DSPF.

Rule-based vs field-solver extraction?

Rule-based precomputed lookup tables use karta hai (fast, full-chip); field-solver Laplace's equation solve karta hai (accurate, critical nets ke liye).

Long global wires buffer/repeater kyun kiye jaate hain?

L^{2}

delay ko chhote segments mein todne ke liye; N segments mein delay

\propto (L / N)^{2} \times N = L^{2} / N

, toh delay buffer count ke saath ~linearly kam hoti hai.

Do wires ke beech (spacing s, thickness t) per length coupling cap?

C_{c} \approx ε t / s

per unit length — facing sidewalls chhote parallel plates ki tarah kaam karte hain.

Recall Feynman: ek 12-saal ke bachhe ko explain karo

Socho tumhari wire ek garden hose hai jo paani (electric current) le jaati hai. Ek perfect hose paani ko instantly through karne deti hai. Lekin real hoses ke andar ki walls par friction hoti hai (yeh resistance, R hai) — yeh flow slow karta hai, lambi thin hoses ke liye aur bhi zyada. Ab socho hose stretchy hai aur doosri hoses se ghiri hai; paani push karne par pehle walls thodi inflate hoti hain flow ke end tak pahunchne se pehle (yeh capacitance, C hai — charge store karna). Ek lambi hose bahut draggy aur bahut stretchy dono hoti hai, aur dono effects multiply hote hain, toh double lambi hose fill hone mein CHAAR guna slow hoti hai. "Parasitic extraction" sirf yeh carefully measure karna hai ki chip mein har hose kitni draggy aur stretchy hai, taaki hum exactly predict kar sakein ki paani kab pahunchega.

Connections

Interconnect delay modeling — jahaan extracted RC delay calc ko feed hota hai.
Elmore delay — RC ladders ka math.
Static Timing Analysis (STA) — SPEF file consume karta hai.
Crosstalk and Signal Integrity — coupling capacitance + Miller se driven.
Repeater / Buffer insertion — $L^{2}$ delay ka fix.
Technology scaling (Dennard) — modern nodes mein wire parasitics dominate kyun karte hain.
Sheet resistance · Parallel-plate capacitor — physics primitives.