Dennard scaling and its breakdown — Hinglish notes

4.2.2 · Hardware › VLSI Design

WHAT is Dennard Scaling?

Idea yeh hai: sab kuch consistently shrink karo (isko constant-field scaling kehte hain) taaki transistor ke andar electric field same rahe. Same field → device physics same behave karta hai, bas chota aur faster.

HOW: Scaling rules ko first principles se derive karna

Hum har geometric dimension ko $1/ k$ se scale karte hain:

Channel length $L \to L / k$
Channel width $W \to W / k$
Oxide thickness $t_{o x} \to t_{o x} / k$
Supply voltage $V \to V / k$ (yeh field ko constant rakhta hai — key trick)

Voltage kyun scale karein? Electric field $\approx V / L$ . Agar hum $L$ ko $k$ se shrink karein par $V$ fixed rakhen, toh field $k$ se jump karta hai → chota transistor fry ho jaata hai. $V$ ko bhi $k$ se scale karne par $E = V / L$ constant rehta hai. Yahi iska "constant field" core hai.

Step 1 — Capacitance

Gate capacitance ek parallel plate hai: $C_{o x} = \frac{ε _{o x} W L}{t _{o x}}$ Yeh step kyun? Yeh woh physical capacitor hai jo gate/oxide/channel se banta hai.

Scale karo: $W \to W / k$ , $L \to L / k$ , $t_{o x} \to t_{o x} / k$ : $C^{'} = \frac{ε _{o x} ( W / k ) ( L / k )}{t _{o x} / k} = \frac{1}{k} C_{o x}$ Toh capacitance $1/ k$ se scale hoti hai. Kyun? Do length shrinks ( $1/ k^{2}$ ) par thinner oxide $C$ ko $k$ se badhata hai → net $1/ k$ .

Step 2 — Current

Drive current (saturation, simplified): $I \approx μ C_{o x}^{''} \frac{W}{L} (V - V_{t h})^{2}, C_{o x}^{''} = \frac{ε _{o x}}{t _{o x}}$ Yeh step kyun? Yeh square-law MOSFET current hai — per second kitna charge move hota hai.

Har factor scale karo: $C_{o x}^{''} \to k C_{o x}^{''}$ (thinner oxide), $W / L$ unchanged, $(V - V_{t h})^{2} \to (1/ k)^{2}$ : $I^{'} = k \cdot 1 \cdot \frac{1}{k ^{2}} I = \frac{1}{k} I$ Toh current $1/ k$ se scale hoti hai.

Step 3 — Delay (speed)

Gate delay $\propto$ capacitance charge karne ka time: $τ = \frac{C V}{I}$ Yeh step kyun? Delay = (move karne wala charge)/(current) = $C V / I$ .

Scale karo: $C \to C / k$ , $V \to V / k$ , $I \to I / k$ : $τ^{'} = \frac{( C / k ) ( V / k )}{I / k} = \frac{1}{k} τ$ Toh delay $1/ k$ se scale hoti hai → frequency $f \to k f$ . Chip $k \times$ faster ho jaati hai. Free.

Step 4 — Power per device

Dynamic power $P = \frac{1}{2} C V^{2} f$ . Par ek clean "per device" number ke liye $P = I V$ use karo: $P^{'} = I^{'} V^{'} = \frac{I}{k} \cdot \frac{V}{k} = \frac{1}{k ^{2}} P$ Toh power per transistor $1/ k^{2}$ se scale hoti hai.

Step 5 — Power density (the punchline)

Area per device $A = W L \to (W / k) (L / k) = A / k^{2}$ . Power density: $\frac{P ^{'}}{A ^{'}} = \frac{P / k ^{2}}{A / k ^{2}} = \frac{P}{A} = CONSTANT$

Formula Dennard scaling table (factor

$k$ )

Quantity	Scales by
Length, width, $t_{o x}$ , $V$	$1/ k$
Capacitance $C$	$1/ k$
Current $I$	$1/ k$
Delay $τ$ / speed	$1/ k$ / $k \times$ faster
Power/device $P$	$1/ k^{2}$
Device density	$k^{2}$
Power density $P / A$	$1$ (constant)

Woh aakhri box hi miracle hai: do gune transistors, do guni speed, same heat per $mm^{2}$ .

Figure — Dennard scaling and its breakdown

WHY it broke (~2005)

Derivation mein assume kiya tha ki $V$ freely shrink ho sakta hai aur transistors puri tarah off ho jaate hain. Dono choti sizes par fail ho jaate hain.

Consequence: power density constant hona band ho gayi aur badhne lagi. Chips ne power wall (~100–150 W/cm², hot plate ke paas) hit kiya. Physically itna cool karna possible nahi.

Worked Examples

Common Mistakes (Steel-manned)

#flashcards/hardware

Dennard scaling transistors shrink hone par kya constant rakhta hai?

Power density (power per unit area),

P / A

"Constant-field" scaling kya hai?

Voltage

V

ko same factor

k

se scale karna jitna dimensions hote hain taaki electric field

E = V / L

constant rahe.

Ideal Dennard scaling of factor

k

ke under gate delay kis factor se scale hoti hai?

1/ k

(chip

k \times

faster),

τ = C V / I

se.

Ideal Dennard mein power per device kis factor se scale hoti hai?

1/ k^{2}

, kyunki

P = I V

aur dono

I, V

scale hote hain

1/ k

se.

Capacitance

1/ k^{2}

nahi,

1/ k

se kyun scale hoti hai?

C = ε W L / t_{o x}

; area

1/ k^{2}

deta hai par thinner oxide

\times k

deta hai → net

1/ k

Kaunsi physical limit ne

V_{t h}

ko scale hone se roka?

Thermal voltage

k T / q \approx 26

mV aur exponential subthreshold leakage

I_{l e ak} \propto e^{- V_{t h} / (nk T / q)}

Jab

V_{t h}

freeze hua toh

V

kyun freeze hua?

Drive current/speed ke liye

V - V_{t h}

headroom chahiye, toh

V

V_{t h}

ke upar ek floor se neeche nahi ja sakta.

"Power wall" kya hai?

~100–150 W/cm² cooling limit jo chips ne hit ki jab power density constant rehna band ho gayi.

Dennard breakdown ka industry ka response kya tha?

Multicore CPUs (moderate clock par zyada cores) high frequency ki jagah; aur 'dark silicon' bhi.

Moore's Law aur Dennard scaling mein kya fark hai?

Moore = transistor count doubles; Dennard = shrink ke dauran power density constant. Dennard pehle mara ~2005.

Agar

V

frozen hai, toh shrink

k

ke saath power density kaise scale hoti hai?

Roughly

k^{3} \times

(current ~

k

se upar, voltage constant, area

k^{2}

se neeche) — yeh badhti hai, power wall cause karti hai.

Recall Feynman: 12-year-old ko explain karo

Transistors ko tiny water taps samjho. Pehle, jab bhi engineers ne taps chote kiye, unhone saath mein water pressure bhi same amount se kam kiya. Result: sink mein kaafi zyada taps fit ho gaye, woh on/off faster switch karte the, aur sink aur garam nahi hoti thi. Free upgrade! Par ek rule hai: ek tap puri tarah off hona chahiye, warna paani leak karta hai aur power waste hoti hai. Off hone ke liye, ek minimum pressure chahiye — ussse neeche nahi ja sakte. Toh pressure stuck ho gayi. Jab pressure kam nahi kar sakte par aur taps thosate rehte ho, toh sink overheating karne lagti hai. Yahi woh waqt hai jab unhone ek super-fast tap ki jagah kai medium taps (cores) laga diye.

Connections

Moore's Law — count scaling; Dennard scaling se zyada jiya.
MOSFET Operation and Square-Law Current — $I \propto (V - V_{t h})^{2}$ ka source.
Subthreshold Leakage and Static Power — $V_{t h}$ kyun nahi gir sakta.
Dynamic vs Static Power — $P_{d y n} = \frac{1}{2} C V^{2} f$ Example 3 mein use hua.
Multicore and Dark Silicon — breakdown ka industry ka jawab.
Power Wall and Thermal Design Power (TDP) — cooling ceiling.
Constant-Field vs Constant-Voltage Scaling — do scaling philosophies.