Static vs dynamic power dissipation — Hinglish notes

3.2.4 · Hardware › CMOS Circuit Design

1. The big picture

$P_{total} = dynamic P_{switching} + P_{short-circuit} + leakage P_{static}$

Figure — Static vs dynamic power dissipation

WHAT har term hai: switching = load caps charge karna; short-circuit = transition ke dauran dono transistors briefly on hona; static = idle hone par leakage.
HOW ye differ karte hain: dynamic activity ke saath scale karta hai (kitni baar switch karte ho) aur frequency ke saath; static hamesha flow karta hai, switching se independent.

2. Dynamic switching power — scratch se derive kiya

WHY it exists: har wire + gate input mein capacitance hoti hai. Output ko HIGH karne ke liye $C_{L}$ par charge dump karna padta hai; LOW karne ke liye wo charge ground par drain karna padta hai. Dono mein energy lagti hai.

Derivation — rising transition par energy. Jab PMOS on hota hai, supply $V_{D D}$ $C_{L}$ ko $0$ se $V_{D D}$ tak charge karta hai.

Supply se li gayi energy: $E_{supply} = \int_{0}^{\infty} V_{D D} i (t) d t = V_{D D} \int_{0}^{\infty} C_{L} \frac{d V _{o u t}}{d t} d t = V_{D D} C_{L} \int_{0}^{V_{D D}} d V_{o u t} = C_{L} V_{D D}^{2}$

Ye step kyu? Cap mein current hai $i = C_{L} d V_{o u t} / d t$ ; substitute karne se time integral ek voltage integral ban jaata hai, aur voltage limits hain $0 \to V_{D D}$ .

Capacitor par end mein stored energy: $E_{stored} = \int_{0}^{V_{D D}} V_{o u t} i d t = C_{L} \int_{0}^{V_{D D}} V_{o u t} d V_{o u t} = \frac{1}{2} C_{L} V_{D D}^{2}$

Toh supply energy ka aadha store hota hai, baaki aadha $\frac{1}{2} C_{L} V_{D D}^{2}$ PMOS resistance mein heat ke roop mein jal jaata hai. Falling edge par stored $\frac{1}{2} C_{L} V_{D D}^{2}$ NMOS ke through heat ban jaata hai.

Energy se power tak. Agar gate $f$ complete cycles per second karta hai: $P_{switching} = C_{L} V_{D D}^{2} f$

Real circuits har clock par toggle nahi karte. Activity factor $α$ introduce karo = probability ki ek node per clock rising transition karta hai:

3. Short-circuit power

WHY: input $V_{T n} < V_{in} < V_{D D} - ∣ V_{T p} ∣$ region se ramp karta hai jahan koi bhi transistor fully off nahi hota. Current $I_{sc}$ seedha flow karta hai.

$P_{sc} \approx α f \overset{ˉ}{I}_{sc} V_{D D} t_{sc}$ jahan $t_{sc}$ input rise/fall time ke proportional hai. HOW to reduce: edges sharp rakho (fast transitions) — slow inputs crowbar window ko bada karte hain. Usually dynamic power ka 5–15%.

4. Static (leakage) power — scratch se

$P_{static} = I_{leak} V_{D D}$

Main leakage sources (WHAT):

Subthreshold leakage — ek transistor "off" ( $V_{GS} < V_{T}$ ) hote hue bhi ek small current pass karta hai jo $V_{T}$ shrink hone par exponentially badhta hai: $I_{s u b} \propto e^{(V_{GS} - V_{T}) / (n V_{t h})}, V_{t h} = \frac{k T}{q} \approx 26 mV at 300 K$ WHY it matters: jaise chips scale hue, engineers ne speed ke liye $V_{T}$ ghataya — jisne $I_{s u b}$ ko exponentially bada kar diya.
Gate-oxide tunneling — electrons ultra-thin gate oxide ke through quantum-tunnel karte hain.
Junction / reverse-bias leakage — reverse-biased diode currents.

HOW to fight it: high- $V_{T}$ transistors, power gating (sleep switches), body biasing, thicker/high- $k$ oxide.

5. Worked examples

6. Common mistakes

7. Forecast-then-Verify

Flashcards

CMOS power dissipation ki do categories kya hain?

Dynamic (switching + short-circuit) aur Static (leakage).

Switching power formula likho.

P = α C_{L} V_{D D}^{2} f

Switching power

V_{D D}^{2}

ke proportional kyu hai?

Ek factor charge

Q = C V

se, ek us voltage se jiske through charge push hoti hai.

C_{L}

V_{D D}

tak charge karne mein kitni energy dissipate hoti hai?

\frac{1}{2} C_{L} V_{D D}^{2}

(supply energy

C_{L} V_{D D}^{2}

ka aadha); baaki aadha cap par store hota hai.

Ek full charge+discharge cycle mein total energy dissipated?

C_{L} V_{D D}^{2}

, transistor resistance se independent.

Kya dissipated switching energy transistor resistance par depend karti hai?

Nahi — R sirf speed (time constant) set karta hai, total energy nahi.

Activity factor

α

kya hai?

Probability ki ek node per clock cycle ek switching (rising) transition karta hai (0–1).

Short-circuit power kis cheez se hoti hai?

NMOS aur PMOS dono input transition ke dauran briefly conduct karte hain,

V_{D D}

-se-GND seedha path dete hain.

Short-circuit power kaise kam karo?

Input rise/fall times fast rakho (sharp edges) taaki crowbar window chhoti rahe.

Teen static leakage mechanisms bataao.

Subthreshold conduction, gate-oxide tunneling, reverse-bias junction leakage.

Subthreshold leakage

V_{T}

par kaise depend karta hai?

Exponentially — lower

V_{T}

(speed ke liye) exponentially zyada leakage cause karta hai.

Static power ka formula?

P_{s t a t i c} = I_{l e ak} V_{D D}

Static power kam karne ki techniques?

High-

V_{T}

transistors, power gating, body biasing, high-k/thicker oxide.

Nanometer nodes mein static power dominant kyu ho gayi?

Scaling ne speed maintain karne ke liye

V_{T}

ghataya, aur subthreshold leakage lower

V_{T}

ke saath exponentially badhti hai.

Recall Feynman: ek 12-saal ke bachche ko samjhao

Socho ek paani ki bucket (wire) hai jise tum baar baar bharte aur khaali karte ho. Dynamic power wo effort hai bucket bharne aur dumping ka — kaam tabhi hota hai jab tum actually paani dalte ho. Paani jitna upar uthao (voltage), utna zyada mushkil hota hai — do guni height matlab chaar guna kaam. Static power bucket mein ek chhota sa chhed hai jo hamesha tappak karta rehta hai, tab bhi jab tum rest kar rahe ho. Purani buckets mein chhed chhota tha; naye super-thin buckets mein chhed zyada leakage karta hai, toh kuch na karte hue bhi paani barbaad hota hai.

Connections

CMOS Inverter operation
Threshold voltage and subthreshold conduction
Voltage scaling and Dennard scaling
Power gating and clock gating
Propagation delay in CMOS
Capacitance in interconnects