Power-delay product — Hinglish notes

3.2.13 · Hardware › CMOS Circuit Design

WHAT hai Power-Delay Product?

Power ko delay se multiply karne par energy kyun milti hai? Power energy-per-second hai ( $P = E / t$ ). Agar ek gate ko switch karne mein $t_{p}$ seconds lagte hain, toh us ek switch ke liye energy hai $E = P \times t_{p}$ . Toh PDP koi arbitrary "figure of merit" nahi hai — yeh ek real physical quantity hai: woh energy jo circuit har baar flip hone par pay karta hai.

HOW karte hain hum PDP derive first principles se (CMOS)

Hum ek CMOS gate ki dynamic energy derive karte hain jo load capacitor $C_{L}$ ko charge karta hai.

Step 1 — Capacitor ko 0 se $V_{D D}$ tak charge karo. Yeh step kyun? CMOS output ka logic-1 tak rise karna matlab PMOS network $C_{L}$ ko $V_{D D}$ tak pull up karta hai. Supply se li gayi energy ka hisaab lagana zaroori hai.

Deliver ki gayi charge: $Q = C_{L} V_{D D}$ . Ek full charge ke dauran supply se li gayi energy: $E_{s u ppl y} = \int_{0}^{\infty} V_{D D} i (t) d t = V_{D D} \int_{0}^{\infty} i d t = V_{D D} Q = C_{L} V_{D D}^{2}$

Step 2 — Woh energy jaati kahan hai? Yeh step kyun? Energy conserve honi chahiye; aadhi store hoti hai, aadhi jalti hai.

Capacitor par store hone wali energy: $E_{c a p} = \frac{1}{2} C_{L} V_{D D}^{2}$ . Charging ke dauran PMOS resistance mein dissipate hone wali energy: $E_{s u ppl y} - E_{c a p} = \frac{1}{2} C_{L} V_{D D}^{2}$ .

Step 3 — Discharge (output 0 par aa jaata hai). Yeh step kyun? Jab output 1→0 jaata hai, toh stored $\frac{1}{2} C_{L} V_{D D}^{2}$ NMOS ke through dump hoti hai aur heat ban jaati hai.

Step 4 — Ek full cycle ki energy (ek up + ek down): $E_{cy c l e} = \frac{1}{2} C_{L} V_{D D}^{2} + \frac{1}{2} C_{L} V_{D D}^{2} = C_{L} V_{D D}^{2}$

Step 5 — Switching frequency $f$ par average dynamic power (activity factor $α$ ): $P_{a v g} = α C_{L} V_{D D}^{2} f$

Frequency term kyun chali gayi? Kyunki PDP per-event energy measure karta hai, power-over-time nahi. Humne deliberately "kitni baar" wala factor hata diya taaki speed-cheating kisi ko faayda na de.

PDP akela kaafi nahi kyun → EDP

Worked Examples

Common Mistakes (Steel-manned)

Recall Feynman: ek 12-saal ke bacche ko samjhao

Socho ek water balloon tap se bharna. Har baar fill karke pop karne par, tum ek fixed cup paani use karte ho — chahe tap kitna bhi fast ya slow kholo. Woh "cup per pop" hi Power-Delay Product hai: ek logic gate ke har flip mein fixed energy per flip. Tap dheere kholo (low voltage) toh har pop mein kam paani, lekin bhrne mein zyada time. Tez kholo toh fast hai lekin zyada waste karta hai. PDP cup ka size batata hai; EDP yeh bhi care karta hai ki tum kitna wait kiye.

Active Recall

PDP physically kis quantity ko represent karta hai?

Har switching event mein dissipate hone wali energy (unit: joules).

CMOS gate ke liye PDP ka clean formula per transition kya hai?

\frac{1}{2} C_{L} V_{D D}^{2}

PDP mein frequency kyun absent hai?

PDP per-event energy hai, power-over-time nahi; frequency hatane se speed metric ko artificially improve nahi kar sakti.

C_{L}

V_{D D}

tak charge karne mein supply kitni energy deliver karta hai?

C_{L} V_{D D}^{2}

(aadhi stored, aadhi PMOS mein jali).

Charging energy ka aadha resistance se independent kyun lost hota hai?

Dissipate hone wali

\frac{1}{2} C_{L} V_{D D}^{2}

sirf

C_{L}

aur

V_{D D}

par depend karti hai; resistance sirf time change karta hai, total energy nahi.

Slow gates ke liye PDP ki blindness kaun sa metric fix karta hai?

EDP = Energy-Delay Product =

P_{a v g} t_{p}^{2}

Agar

V_{D D}

half ho jaaye, toh PDP kaise change hoga?

Yeh one-quarter ho jaata hai (PDP

\propto V_{D D}^{2}

PDP ki units kya hain?

Joules (energy), kyunki W × s = J.

Average dynamic power formula kya hai?

P_{a v g} = α C_{L} V_{D D}^{2} f

Connections

Dynamic power dissipation
CMOS Inverter
Propagation delay
Energy-delay product (EDP)
Voltage scaling / DVFS
Switching activity factor
RC charging energy