Logic gate propagation delay: Exercises — Hardware deep dive

The tools we lean on: the charging law $V (t) = V_{D D} (1 - e^{- t / R C_{L}})$ , the core delay result $t_{p d} \approx 0.69 R C_{L}$ , and the rule that delays add along a path. See also RC circuits and time constant, Fan-out and loading, Critical path and clock frequency, and Static and dynamic hazards.

Level 1 — Recognition

L1·Q1

Which reference points on the input and output waveforms are used to define propagation delay?

Recall Solution

The 50% voltage level of the input to the 50% voltage level of the output. Why 50%? The logic threshold — the voltage the next gate uses to decide 0 vs 1 — sits about halfway up the swing, so 50% is a consistent, technology-independent marker.

L1·Q2

A gate's output goes from Low to High in response to an input change. Which delay symbol is this, $t_{p L H}$ or $t_{p H L}$ ?

Recall Solution

$t_{p L H}$ — the letters name the output transition: Low → High.

L1·Q3

True or false: a truth table tells you when the output settles.

Recall Solution

False. A truth table is timeless — it only states what the steady-state output is, never when it arrives. Timing is a separate layer, given by $t_{p d} \approx 0.69 R C_{L}$ .

Level 2 — Application

L2·Q1

A CMOS inverter has pull-down resistance $R = 4 k Ω$ and load $C_{L} = 15 fF$ . Find its time constant $τ$ and its $t_{p H L}$ .

Recall Solution

Step 1 — the time scale. $τ = R C_{L} = 4000 \times 15 \times 1 0^{- 15} = 6.0 \times 1 0^{- 11} s = 0.06 ns$ . Why? $τ$ sets the whole clock of the exponential charge/discharge. Step 2 — the 50% crossing. $t_{p H L} = 0.69 τ = 0.69 \times 0.06 = 0.0414 ns = 41.4 ps$ . Why? Delay is the time to reach $V_{D D} /2$ , which costs a factor $ln 2 \approx 0.69$ .

L2·Q2

A driver has $R = 2 k Ω$ . It must charge $C_{L} = 50 fF$ within $t_{p d} = 60 ps$ . Does it meet the budget?

Recall Solution

Step 1. $t_{p d} = 0.69 R C_{L} = 0.69 \times 2000 \times 50 \times 1 0^{- 15} = 6.9 \times 1 0^{- 11} s = 69 ps$ . Step 2. $69 ps > 60 ps$ , so it fails the budget by $9 ps$ . Why? The required delay is smaller than the delivered delay; the driver is too slow for this load.

L2·Q3

Fan-out doubles: a gate that drove $C_{L} = 10 fF$ now drives $20 fF$ (nothing else changes). By what factor does its delay change, and why?

Recall Solution

Step 1. $t_{p d} = 0.69 R C_{L}$ is linear in $C_{L}$ . Step 2. Doubling $C_{L}$ doubles $t_{p d}$ — factor 2×. Why? Twice the charge must be pushed through the same resistance, so it takes twice as long to reach the halfway voltage. See Fan-out and loading.

Level 3 — Analysis

L3·Q1

A signal passes through three gates on one path: XOR ( $5 ns$ ) → NAND ( $2 ns$ ) → INV ( $1 ns$ ). Find the total path delay and the maximum clock frequency if this is the critical path.

Recall Solution

Step 1 — delays add. $5 + 2 + 1 = 8 ns$ . Why? Each gate cannot begin responding until its input (the previous gate's output) has settled; the waits stack up in series. Step 2 — frequency limit. $f_{ma x} = \frac{1}{t _{cr i t i c a l}} = \frac{1}{8 \times 1 0 ^{- 9}} = 1.25 \times 1 0^{8} Hz = 125 MHz$ . Why? A fresh input can't be launched faster than the output settles. See Critical path and clock frequency.

L3·Q2

A circuit has two paths from input to output: Path A = AND( $3$ ) → OR( $2$ ) → INV( $1$ ), all in ns. Path B = NAND( $4$ ) → NAND( $4$ ), in ns. Which path is critical, and what is $f_{ma x}$ ?

Recall Solution

Step 1 — sum each path. Path A $= 3 + 2 + 1 = 6 ns$ . Path B $= 4 + 4 = 8 ns$ . Step 2 — pick the longest. The critical path is the slower one: Path B, $8 ns$ . Why? The output is only guaranteed correct once every path has settled — the slowest one dominates. Step 3. $f_{ma x} = 1/ (8 \times 1 0^{- 9}) = 125 MHz$ .

L3·Q3

Compute $Y = A \cdot \overline{A}$ where the inverter that produces $\overline{A}$ has $3 ns$ delay and the AND gate is ideal (0 delay). Let $A$ go $0 \to 1$ at $t = 0$ . Describe the output over time.

Recall Solution

Step 1 — before the switch. For $t < 0$ : $A = 0$ , $\overline{A} = 1$ , so $Y = 0 \cdot 1 = 0$ . ✓ Step 2 — just after the switch. At $t = 0^{+}$ : $A = 1$ now, but $\overline{A}$ is still 1 because the inverter's output won't fall until $3 ns$ have passed. Step 3 — the glitch. During $0 < t < 3 ns$ : $Y = 1 \cdot 1 = 1$ — a false 1 pulse of width $\approx 3 ns$ . Step 4 — after settling. For $t > 3 ns$ : $\overline{A} = 0$ , so $Y = 1 \cdot 0 = 0$ . ✓ Why? Unequal arrival times at the AND gate produce a momentary wrong output — a static-1 hazard. See Static and dynamic hazards.

Level 4 — Synthesis

L4·Q1

A driver must meet $t_{p d} \leq 40 ps$ while driving $C_{L} = 30 fF$ . What is the maximum allowable pull-down resistance $R$ ?

Recall Solution

Step 1 — rearrange the core formula. $t_{p d} = 0.69 R C_{L} \Rightarrow R = \frac{t _{p d}}{0.69 C _{L}}$ . Step 2 — plug in. $R = \frac{40 \times 1 0 ^{- 12}}{0.69 \times 30 \times 1 0 ^{- 15}} = \frac{40 \times 1 0 ^{- 12}}{2.07 \times 1 0 ^{- 14}} \approx 1932 Ω \approx 1.93 k Ω.$ Why? Lower $R$ means faster; the largest $R$ that still meets the budget is the equality case.

L4·Q2

A chain of $N$ identical inverters, each with $t_{p d} = 25 ps$ , must have total delay below $200 ps$ . What is the maximum $N$ ?

Recall Solution

Step 1 — total delay. $N$ identical stages in series give $N \times 25 ps$ . Step 2 — inequality. $25 N < 200 \Rightarrow N < 8$ . Step 3 — integer. The largest integer below 8 is $N = 7$ ( $7 \times 25 = 175 ps < 200$ ; $8 \times 25 = 200$ is not below 200). Why? "Below" is a strict inequality, so $N = 8$ (exactly 200 ps) is excluded.

L4·Q3

Two design options for one driver stage:

Option A: $R = 6 k Ω$ , self input-capacitance $= 4 fF$ .
Option B: $R = 3 k Ω$ , self input-capacitance $= 8 fF$ (bigger transistor).

Each drives an external load $C_{e x t} = 12 fF$ . But the previous stage has $R_{p r e v} = 5 k Ω$ and must charge this stage's input capacitance. Compare the total delay (previous stage delay + this stage delay) for both options.

Recall Solution

This stage drives only the external load $C_{e x t} = 12 fF$ (its own input cap is a load on the previous stage, not itself). Option A

This stage: $t = 0.69 \times 6000 \times 12 \times 1 0^{- 15} = 49.68 ps$ .
Previous stage charging A's input (4 fF): $t = 0.69 \times 5000 \times 4 \times 1 0^{- 15} = 13.8 ps$ .
Total $= 49.68 + 13.8 = 63.48 ps$ . Option B
This stage: $t = 0.69 \times 3000 \times 12 \times 1 0^{- 15} = 24.84 ps$ .
Previous stage charging B's input (8 fF): $t = 0.69 \times 5000 \times 8 \times 1 0^{- 15} = 27.6 ps$ .
Total $= 24.84 + 27.6 = 52.44 ps$ . Verdict: Option B is faster overall ( $52.44 < 63.48$ ps) — its lower $R$ more than pays for the extra input capacitance it imposes on the previous stage. Why? Sizing is a trade-off: you must count the delay you add upstream, not just the delay you save locally. See Fan-out and loading and CMOS transistor structure.

Level 5 — Mastery

L5·Q1

Derive the exact factor for a 10%–90% rise time from the charging law, and compare it to the propagation-delay factor. (Show that $t_{r}$ uses a different constant than $0.69$ .)

Recall Solution

Step 1 — the law. $V (t) = V_{D D} (1 - e^{- t / R C})$ , so $\frac{V}{V _{D D}} = 1 - e^{- t / R C}$ . Step 2 — time to 10%. $0.1 = 1 - e^{- t_{10} / R C} \Rightarrow e^{- t_{10} / R C} = 0.9 \Rightarrow t_{10} = R C ln (1/0.9) = R C ln (10/9)$ . Step 3 — time to 90%. $0.9 = 1 - e^{- t_{90} / R C} \Rightarrow e^{- t_{90} / R C} = 0.1 \Rightarrow t_{90} = R C ln (10)$ . Step 4 — rise time. $t_{r} = t_{90} - t_{10} = R C [ln 10 - ln \frac{10}{9}] = R C ln 9 \approx 2.197 R C .$ Compare: rise time uses $\approx 2.20 R C$ , propagation delay uses $0.69 R C$ . They measure different things — edge sharpness vs 50% arrival — so of course the constants differ. This is exactly why you must never confuse them.

L5·Q2

Consider the degenerate/limiting cases of $t_{p d} = 0.69 R C_{L}$ : (a) $C_{L} \to 0$ (no load at all), (b) $R \to 0$ (perfect switch), (c) $R \to \infty$ (transistor barely conducts). What delay does each predict, and is it physical?

Recall Solution

(a) $C_{L} \to 0$ : $t_{p d} \to 0$ . With nothing to charge, the output flips essentially instantly. Idealised limit — real gates always have some internal parasitic capacitance, so true delay never hits exactly zero. (b) $R \to 0$ : $t_{p d} \to 0$ again — a perfect (zero-resistance) switch dumps charge onto $C_{L}$ instantly. Idealised — real transistors always have finite channel resistance. (c) $R \to \infty$ : $t_{p d} \to \infty$ — a transistor that barely conducts takes forever to charge the load. This is the failure mode of an under-driven or "off" transistor: the output never reaches threshold in useful time. Why these matter: they confirm the formula behaves sensibly — delay vanishes when there is nothing to charge or no resistance, and blows up when conduction dies. See RC circuits and time constant.

L5·Q3

A gate's delay is specified as the average $t_{p d} = \frac{1}{2} (t_{p L H} + t_{p H L})$ . A particular inverter has pull-up resistance $R_{p} = 10 k Ω$ and pull-down resistance $R_{n} = 5 k Ω$ , both driving the same $C_{L} = 8 fF$ . Find $t_{p L H}$ , $t_{p H L}$ , and the quoted average $t_{p d}$ .

Recall Solution

Step 1 — Low→High uses the pull-up. Charging up to $V_{D D}$ goes through $R_{p}$ : $t_{p L H} = 0.69 \times 10000 \times 8 \times 1 0^{- 15} = 55.2 ps$ . Step 2 — High→Low uses the pull-down. Discharging to ground goes through $R_{n}$ : $t_{p H L} = 0.69 \times 5000 \times 8 \times 1 0^{- 15} = 27.6 ps$ . Step 3 — average. $t_{p d} = \frac{1}{2} (55.2 + 27.6) = 41.4 ps .$ Why the two differ: the rising and falling edges are driven by different transistors with different resistances, so the two delays are genuinely unequal. The single quoted number is their average. This asymmetry (a fatter pull-up because holes are slower carriers) traces back to CMOS transistor structure.

Active recall

Recall Rapid self-check

State the 50%→50% definition without looking. ::: Input crosses 50% of its swing to output crosses 50%, in response to that change.
$t_{p d}$ in terms of $R$ and $C_{L}$ ? ::: $t_{p d} \approx 0.69 R C_{L}$ .
Do parallel paths add or take the max? ::: Take the max (critical path); within one path they add.
Why is $t_{p L H} \neq = t_{p H L}$ ? ::: Rise and fall use different transistors (pull-up vs pull-down) with different resistances.

Connections

3.1.15 — Parent topic
Boolean Algebra & Logic Gates — the timeless logic layer these delays sit on
RC circuits and time constant — where $0.69 R C$ comes from
CMOS transistor structure — source of $R$ and $C_{L}$ , and of the rise/fall asymmetry
Fan-out and loading — why $C_{L}$ grows with driven gates
Critical path and clock frequency — how path delays set $f_{ma x}$
Static and dynamic hazards — glitches from unequal delays