Logic gate propagation delay: Visual walkthrough — Hardware deep dive

Step 1 — What is actually inside a gate?

WHAT. A logic gate does not compute with magic. Its output wire is connected to a switch made of transistors (see CMOS transistor structure). When the switch closes, it connects the output wire either up to the power supply (a high voltage we call $V_{D D}$ ) or down to ground ( $0$ volts).

WHY. Before we can talk about time, we must know what physical thing is moving. The thing that moves is electric charge, flowing onto or off the output wire. Nothing about the truth table tells us this — the truth table only says the final answer, never how the wire gets there.

PICTURE. Below: the gate on the left, its output wire in the middle, and the "stuff hanging off that wire" on the right. That stuff is what we must charge.

Step 2 — The wire behaves like a tiny bucket (capacitance)

WHAT. Every wire, and the input of every gate it feeds, stores a little charge when you raise its voltage. We lump all of that into one number: the load capacitance $C_{L}$ .

WHY this idea, not another? We need a way to say "how much charge do I have to deliver to raise this wire by one volt?" That is exactly what capacitance means. A capacitor is defined by:

$charge stored (coulombs) Q = capacitance (farads) C_{L} \times voltage across it (volts) V$

Read it as a bucket: $C_{L}$ is how wide the bucket is. A wide bucket needs a lot of water (charge) to raise the level (voltage) even a little. This is why fan-out costs time — more gates on the wire = a wider bucket. (See Fan-out and loading.)

PICTURE. The wire drawn as a bucket. Wide bucket = big $C_{L}$ = slow to fill.

Step 3 — The transistor is a resistor (the narrow straw)

WHAT. The closed transistor is not a perfect wire. It has a resistance $R$ (its "on resistance"). Charge must squeeze through it to reach the bucket.

WHY this tool — Ohm's law? We need to know how much current actually flows for a given push. The push available is the voltage still remaining between the supply and the wire, namely $V_{D D} - V$ . Ohm's law answers exactly "current from a voltage across a resistance":

$current through the straw I = \frac{V _{D D} - V voltage still left to push with}{straw narrowness R}$

Notice the built-in slowdown: as the bucket fills ( $V$ rises toward $V_{D D}$ ), the leftover push $V_{D D} - V$ shrinks, so the current shrinks — the last bit fills slowest. (For the same physics in a pure-circuits setting, see RC circuits and time constant.)

PICTURE. The straw between supply and bucket; the arrow shrinks as the bucket fills.

Step 4 — Join the two facts into one equation

WHAT. The same current flows through the straw and into the bucket (one path, nowhere else to go). So set the two expressions for $I$ equal:

$current filling the bucket C_{L} \frac{d V}{d t} = current through the straw \frac{V _{D D} - V}{R}$

WHY. This is just conservation of charge (Kirchhoff's current law): what leaves the resistor must enter the capacitor. Now we have one equation relating $V$ and how fast it changes — that is enough to pin down $V (t)$ completely.

PICTURE. The full loop: supply → straw ( $R$ ) → bucket ( $C_{L}$ ) → ground, with the shared current.

Step 5 — Solve it: the easing curve

WHAT. We want $V$ as a function of $t$ . Rearrange the equation so all the $V$ 's are on one side and all the $t$ 's on the other (this is separating variables — allowed because each side then depends on only one letter):

$\frac{d V}{V _{D D} - V} = \frac{d t}{R C _{L}}$

Add up (integrate) both sides from the start ( $V = 0$ at $t = 0$ ). The left side is a standard sum that produces a logarithm, $- ln (V_{D D} - V)$ .

WHY does a logarithm appear? Because the rate of change is proportional to the amount remaining — that is the fingerprint of exponential behaviour, and its integral is always a log. Undoing the log (applying $e^{\cdot}$ to both sides) gives:

$V (t) = target V_{D D} (1 - fraction still missing at time t e^{- t / τ})$

Reading it term by term.

At $t = 0$ : $e^{0} = 1$ , so $V = V_{D D} (1 - 1) = 0$ . ✔ starts empty.
As $t \to \infty$ : $e^{- \infty} = 0$ , so $V \to V_{D D}$ . ✔ fills all the way, but never jumps.
At $t = τ$ : $e^{- 1} \approx 0.37$ , so $V \approx 0.63 V_{D D}$ — 63% full after one time constant.

PICTURE. The rising curve, flattening as it approaches $V_{D D}$ . Mark the $63%$ point at $τ$ .

Step 6 — Where does 0.69 come from? (the 50% crossing)

WHAT. Delay is defined as the time for the output to reach half of the supply, $V = \frac{1}{2} V_{D D}$ — the level at which the next gate flips its decision from 0 to 1. Set $V = V_{D D} /2$ and solve for $t$ :

$\frac{V _{D D}}{2} = V_{D D} (1 - e^{- t / τ}) \Rightarrow e^{- t / τ} = \frac{1}{2} \Rightarrow t = τ ln 2$

WHY 50%, and why does $ln 2$ pop out? We ask "when is the bucket half full?" The missing fraction $e^{- t / τ}$ must equal $\frac{1}{2}$ . Undoing the exponential with its inverse, $ln$ , gives $t / τ = ln 2$ . The number $ln 2 \approx 0.693$ is simply "how many time constants to fill half the bucket."

PICTURE. Same curve, now with the horizontal line at $50%$ and the vertical drop marking $t_{p d} = 0.69 τ$ .

Step 7 — The two directions, and the degenerate cases

WHAT. Two things can happen and two edge cases must be checked.

Output rising (Low→High): the curve above; delay is $t_{p L H}$ .
Output falling (High→Low): the mirror image — the bucket drains through a (possibly different) resistor, following $V (t) = V_{D D} e^{- t / τ}$ , hitting 50% again at $t_{p H L} = 0.69 τ$ . Because pull-up and pull-down transistors differ, $R$ (hence the delay) can differ each way — that is why we average: $t_{p d} = \frac{1}{2} (t_{p L H} + t_{p H L})$ .

Degenerate cases — check the formula never breaks:

$C_{L} \to 0$ (no load at all): $t_{p d} = 0.69 R \cdot 0 = 0$ . Instant. ✔ matches intuition (empty bucket fills immediately).
$R \to 0$ (perfect wire, infinitely strong transistor): $t_{p d} = 0$ . ✔ Also instant — but real transistors can never reach $R = 0$ , and a stronger one costs input capacitance for the previous stage (see Fan-out and loading).
Unequal arrival at a downstream gate: if two inputs to one gate carry different delays, the gate momentarily sees a wrong combination → a false pulse. That is a static hazard (see Static and dynamic hazards).

PICTURE. Rising vs falling curves mirrored, both crossing 50% at $0.69 τ$ ; a small inset shows the glitch from mismatched delays.

Step 8 — Delays add along a path

WHAT. Chain gates in a line. Each gate cannot begin its own $0.69 R C$ climb until its input (the previous output) has already reached 50%. So the finish times stack end-to-end:

$t_{path} = t_{1} + t_{2} + \dots + t_{n}, f_{ma x} \leq \frac{1}{t _{path}}$

WHY sum, not average? Each stage's start is the previous stage's finish — waiting times are sequential, so they add. The longest such chain is the critical path, and it caps the clock (see Critical path and clock frequency).

PICTURE. Three gate curves shifted in time, each starting where the last hit 50%; total time bracketed at the bottom.

The one-picture summary

Everything above in a single frame: a bucket (width $C_{L}$ ) being filled through a straw (narrowness $R$ ) from a tank at height $V_{D D}$ ; the resulting easing curve; the 50% line; and the label $t_{p d} = 0.69 R C_{L}$ at the crossing.

Recall Feynman: tell the whole walkthrough in plain words

A gate's output wire is like an empty cup. The transistor that just switched on is a thin straw connecting the cup to a full water tank (the power supply, height $V_{D D}$ ). Charge is the water. How wide the cup is, is $C_{L}$ ; how thin the straw is, is $R$ . When you open the straw, water rushes in fast at first — big height difference, big push — then slower and slower as the cup fills and the leftover push shrinks. That slowing-down shape is the exponential $V_{D D} (1 - e^{- t / τ})$ , and $τ = R C_{L}$ is its natural clock. The next gate only "reads a 1" once the cup is half full, and reaching half takes $ln 2 \approx 0.69$ of those clock-ticks: $t_{p d} = 0.69 R C_{L}$ . Fatten the straw (smaller $R$ ) or shrink the cup (smaller $C_{L}$ ) and it fills sooner. Line many cups-and-straws up and the waiting times add — that longest line is the critical path that sets how fast the whole chip can be clocked.

Recall Quick self-test

Where does the number 0.69 come from? ::: From solving $e^{- t / τ} = \frac{1}{2}$ for the 50% crossing: $t = τ ln 2$ , and $ln 2 \approx 0.693$ . Why does the charging current shrink over time? ::: The push is $V_{D D} - V$ ; as $V$ rises the leftover push falls, so $I = (V_{D D} - V) / R$ falls. What physical meaning does $τ = R C_{L}$ carry? ::: The natural time scale; after one $τ$ the output is 63% of the way to $V_{D D}$ . Why do path delays add rather than average? ::: Each gate starts only when the previous output hits 50%, so finish times are sequential and stack.

Connections

Logic gate propagation delay — the parent result this page derives visually
CMOS transistor structure — where $R$ and $C_{L}$ physically come from
RC circuits and time constant — the same charging equation in pure circuit form
Fan-out and loading — why more driven gates means bigger $C_{L}$
Static and dynamic hazards — glitches from unequal path delays
Critical path and clock frequency — why the longest summed path caps the clock