Logic gate propagation delay: Question bank — Hardware deep dive

For the numbers-and-formulas drills see the computation banks; here we chase understanding.

True or false — justify

A logic gate's truth table already tells you when the output changes

False — a truth table is timeless; it only states the steady-state value, never the moment it arrives. Timing (delay) is a separate physical layer laid on top of the logic.

Propagation delay is measured from the start of the input edge to the start of the output edge

False — it is 50%-to-50% between the two signals. The "start" of an exponential is ambiguous, so the halfway logic threshold is used as a technology-neutral reference.

If two gates have the same

t_{p d}

they will always produce identically timed edges

False —

t_{p d}

is the 50%-crossing delay, but their rise/fall sharpness (10%–90% transition time) can differ. Same delay does not mean same edge shape.

Doubling the load capacitance

C_{L}

roughly doubles the delay

True — since

t_{p d} \approx 0.69 R C_{L}

, delay is linear in

C_{L}

, so twice the load is about twice the delay. (See Fan-out and loading.)

Doubling the supply voltage

V_{D D}

doubles the delay because there's more voltage to climb

False — the 50% target scales with

V_{D D}

too, so

t_{p d} = R C_{L} ln 2

is independent of

V_{D D}

in this simple model. The halfway point is always reached at the same fraction of

τ

Total delay through a chain of gates is the average of their individual delays

False — delays along one path add. And you care about the longest (critical) path, not a typical one. (See Critical path and clock frequency.)

A wider (stronger) driver transistor always speeds up the whole circuit

False — it lowers its own

R

, but it presents a larger input capacitance to the previous stage, slowing that gate. Sizing is a trade-off, not free speed.

The maximum clock frequency is at most

1/ t_{cr i t i c a l p a t h}

True — a new input cannot be launched until the previous result has settled through the slowest path, so the clock period must be at least the critical-path delay.

Rise/fall time and propagation delay are just two names for the same thing

False — propagation delay is 50%(in)→50%(out) between two signals; rise/fall time is 10%→90% of one signal. One measures lateness, the other measures edge sharpness.

t_{p L H}

and

t_{p H L}

are always equal

False — the pull-up path and pull-down path in CMOS have different effective resistances, so the L→H and H→L delays usually differ. We often just quote their average

t_{p d}

Spot the error

"Since the gate 'knows' the correct output instantly,

t_{p d} = 0

The gate knows the value instantly, but moving charge onto

C_{L}

through resistance

R

takes time — about

0.69 R C_{L}

. Logic is instant; physics is not.

"I'll measure delay at the 0% points so I capture the whole edge."

An exponential never has a sharp 0% "start", so that point is undefined and non-repeatable. That's exactly why 50% is the standard, unambiguous reference.

"Longer wires don't matter to a signal's timing."

A longer wire adds capacitance to

C_{L}

(and resistance), increasing

τ = R C_{L}

and hence delay. Wire length is a real timing cost. (See RC circuits and time constant.)

"A glitch means my Boolean logic is wrong."

The logic can be perfectly correct; a static hazard is a purely delay-caused false pulse when two inputs to a gate arrive at different times. It's a timing artefact, not a logic error. (See Static and dynamic hazards.)

"The output voltage jumps straight to

V_{D D}

the instant the input switches."

It follows

V (t) = V_{D D} (1 - e^{- t / R C_{L}})

— it eases up exponentially, never jumping. That easing is the whole reason delay exists.

Y = A \cdot \overline{A}

is always 0, so it can never produce a pulse."

In steady state it is 0, but the inverter's delay makes

\overline{A}

lag, so for a moment

A = 1

and

\overline{A} = 1

still — a glitch. Boolean simplification hides the timing.

Why questions

Why is the 50% voltage level chosen as the reference for delay?

Because the next gate's logic threshold (where it decides 0 vs 1) sits roughly halfway, so 50% is where "the signal has effectively arrived" in a technology-independent way.

Why does the factor

0.69

(not

1

) appear in

t_{p d} = 0.69 R C_{L}

Because delay is timed to the 50% crossing: setting

V = V_{D D} /2

in the charging curve gives

e^{- t / R C_{L}} = \frac{1}{2}

, so

t = R C_{L} ln 2 \approx 0.69 R C_{L}

Why does higher fan-out slow a gate down?

Each driven gate adds its input capacitance to the load

C_{L}

; since delay

\propto C_{L}

, more fan-out means a bigger cup to fill, hence more delay.

Why do delays add along a path instead of overlapping?

A gate cannot begin responding until its input (the previous gate's output) has settled, so each stage waits for the one before it — the waits stack end-to-end.

Why is a purely exponential model enough to predict "delay grows with

R

and

C_{L}

Because the time constant is

τ = R C_{L}

, and the 50% delay is a fixed multiple of

τ

; so both

R

and

C_{L}

scale the delay linearly regardless of the finer details.

Why can equalising path delays remove a static hazard?

The glitch comes from two inputs of a gate arriving at different times; if their path delays match, they change simultaneously and no false intermediate combination occurs.

Edge cases

C_{L} = 0

(ideal zero load), what happens to

t_{p d}

Then

τ = R C_{L} = 0

, so

t_{p d} = 0.69 R C_{L} = 0

— instantaneous in the model. Real circuits always have some parasitic capacitance, so this is only a limiting ideal.

If the driver's ON-resistance

R \to 0

(a perfect switch), what is the delay?

t_{p d} = 0.69 R C_{L} \to 0

as well. With no resistance to limit current, the capacitor charges instantly — again an idealisation, not achievable in silicon.

As time

t \to \infty

, does the output ever exactly reach

V_{D D}

No —

V (t) = V_{D D} (1 - e^{- t / R C_{L}})

approaches

V_{D D}

asymptotically but never mathematically equals it. It just gets close enough to read reliably long before then.

What is the delay of a chain if every gate on it has zero delay?

Zero — the sum of zeros is zero, so the critical-path delay vanishes and

f_{ma x}

is unbounded in the model. Impossible physically, but it shows delay is strictly additive.

For a single gate driving a single identical gate versus driving eight, how does the delay compare?

Driving eight loads adds roughly eight input capacitances to

C_{L}

, so the delay is much larger (up to ~8× the capacitive contribution). This is the concrete cost of fan-out.

If a signal could take two different paths to the same output, which delay determines when the output is finally stable?

The longer path — the output isn't guaranteed correct until the slowest contribution has arrived, which is exactly the critical-path idea.

Recall One-line self-test before leaving

Delay is measured 50%-to-50%, gives factor == $0.69 = ln 2$ , and delays add along the critical== path.

Connections

Logic gate propagation delay — the parent concept this bank interrogates
Fan-out and loading — why more loads mean more $C_{L}$ and more delay
Critical path and clock frequency — why the longest path sets $f_{ma x}$
Static and dynamic hazards — the glitch traps above
CMOS transistor structure — source of $R$ and $C_{L}$
RC circuits and time constant — the exponential charging behind it all