Logic gate propagation delay: Foundations — Hardware deep dive

This page assumes you know nothing. We build every letter, squiggle, and word the parent note uses, in an order where each one only needs the ones before it. By the end you will be able to read the whole delay derivation without meeting a single surprise.

0. What a "signal" even is

Before any symbol, picture the thing that moves: a voltage on a wire.

Why the topic needs it: propagation delay is defined by when a voltage reaches a certain height. No notion of voltage, no notion of "the output changed."

1. $V_{D D}$ — the supply voltage (the full-tank level)

Picture the red dashed line at the very top of the tank in the figure above. Everything the output does happens between 0 and $V_{D D}$ .

Why the topic needs it: the charging equation asks "how long to rise from 0 up toward $V_{D D}$ ?" — you cannot ask that without naming the top.

2. The 50% level and the 10%/90% levels

Why the topic needs it: propagation delay is measured 50%-in to 50%-out; rise/fall time is measured 10%-to-90% of one signal. Confusing these two is a classic mistake — so we nail the pictures now.

3. Capacitance $C_{L}$ — the size of the bucket

Why the topic needs it: delay grows linearly with $C_{L}$ . Bigger bucket → longer to fill → slower gate. This is the whole reason fan-out costs time (see Fan-out and loading).

4. Resistance $R$ — how narrow the pipe is

Why the topic needs it: delay grows linearly with $R$ too. Narrower straw → slower fill → slower gate. Making the transistor bigger lowers $R$ (faster) but enlarges its own input capacitance (slower for whatever drives it) — the trade-off the parent warns about.

5. Current $I$ — the flow itself

Why the topic needs it: the derivation starts by saying "the same current flows through the straw and into the bucket." That single sentence is the whole physics; everything else is algebra.

6. The derivative $\frac{d V}{d t}$ — "how fast is the level rising right now?"

Here a mathematical tool enters. We must earn it.

Why the topic needs it: a capacitor's current is by definition $I = C \frac{d V}{d t}$ . Without the derivative we cannot even write the governing equation.

7. The time constant $τ = R C_{L}$ — the natural clock of the fill

Why the topic needs it: every delay number is just a multiple of $τ$ . The famous result $t_{p d} \approx 0.69 R C_{L}$ is simply $0.69 τ$ . See RC circuits and time constant for the full behaviour.

8. The exponential $e^{- t / τ}$ and the logarithm $ln$

Two more tools; both earned by the shape of the fill.

Why the topic needs it: the exponential is the charging curve; the logarithm is how you read a time off it. No other pair of tools answers "when does the eased-up curve cross halfway?"

9. $t_{p d}$ , $t_{p L H}$ , $t_{p H L}$ — naming the delays

Why the topic needs it: filling and draining can take different times (different transistors, different $R$ ), so we keep separate names — and unequal delays are exactly what cause the glitches in Static and dynamic hazards.

10. $f_{ma x}$ — turning delay into speed

Why the topic needs it: this is why delay matters — it caps how fast the whole machine can run. See Critical path and clock frequency.

How these foundations feed the topic

Equipment checklist

Cover the right side and test yourself.

What does the symbol $V$ measure, and what is its "water" picture? ::: Voltage — the electrical "height" or water level on a wire; high = logic 1, low = logic 0.
What is $V_{D D}$ ? ::: The fixed supply voltage — the ceiling the output rises toward, counted as a solid logic 1.
Why is delay measured at the 50% point and not 0% or 100%? ::: 50% is the logic threshold where the next gate decides 0 vs 1 — a technology-neutral, unambiguous reference; the exponential has no clear "start."
What does capacitance $C_{L}$ physically mean? ::: How much charge must flow in to raise the voltage by one volt — the size of the "bucket"; bigger $C_{L}$ = slower.
What is $R$ in a CMOS gate, and what picture is it? ::: The ON-resistance of the switching transistor — the "narrow straw" that limits current; bigger $R$ = slower.
State the defining law of a capacitor's current. ::: $I = C \frac{d V}{d t}$ — current equals capacitance times the instantaneous rate of voltage change.
Why must we use the derivative $\frac{d V}{d t}$ instead of $Δ V /Δ t$ ? ::: Charging speed is not constant (starts fast, slows down); the derivative gives the rate at each instant, which is what we need.
What is the time constant $τ$ , and how full is the bucket after one $τ$ ? ::: $τ = R C_{L}$ ; after one $τ$ the output has reached about 63% of $V_{D D}$ .
Why does the charging curve use $e^{- t / τ}$ ? ::: Because the fill rate is proportional to how much is left to do — the signature situation that produces an exponential.
What does $ln$ do, and why do we need it here? ::: It undoes $e$ (asks " $e$ to what power?"); we need it to solve for the time $t$ trapped inside the exponent when finding the 50% crossing.
Where does the number 0.69 come from? ::: From $ln 2 \approx 0.693$ , since reaching 50% means $e^{- t / τ} = \frac{1}{2} \Rightarrow t = τ ln 2$ .
Distinguish $t_{p L H}$ from $t_{p H L}$ . ::: $t_{p L H}$ = output Low→High (bucket filling); $t_{p H L}$ = output High→Low (bucket draining); they can differ.
How does $f_{ma x}$ relate to delay? ::: $f_{ma x} \leq 1/ t_{critical path}$ — you cannot clock faster than the slowest path settles.

Connections

Parent: Propagation delay — the topic all these symbols build
Boolean Algebra & Logic Gates — the timeless logic layer beneath the timing
CMOS transistor structure — where the resistor $R$ and bucket $C_{L}$ physically come from
RC circuits and time constant — the full life of $τ$ , $e^{- t / τ}$ , and charging
Fan-out and loading — why driving more gates enlarges $C_{L}$
Static and dynamic hazards — glitches born from unequal delays
Critical path and clock frequency — turning summed delays into $f_{ma x}$