Logic gate propagation delay: Worked examples — Hardware deep dive

Before we start, every symbol we use — earned once, then reused:

The picture first: straw, cup, and the rising curve

Before any algebra, look at what is physically happening. The switching transistor is a resistor $R$ (the thin straw); the output node is a capacitor $C_{L}$ (the cup); the supply $V_{D D}$ is the water tap. When the gate flips, charge must flow through the straw to fill the cup — and that takes time.

The left panel is the actual circuit ("straw and cup"): current $i$ flows from $V_{D D}$ through the red resistor $R$ onto the blue capacitor $C_{L}$ , whose voltage $V$ is the gate output. The right panel is the story over time — trace the yellow curve rising from $0$ and easing toward the dotted $V_{D D}$ line. The output never jumps; it climbs an exponential. Where the yellow curve crosses the blue 50% line (the pink dot) is the moment we call the delay: $t = τ ln 2 \approx 0.69 τ$ . Keep this picture in your head — every example below is just this curve read at a different height or a different $R$ and $C_{L}$ .

The scenario matrix

Every propagation-delay question is one of the cells below. The flowchart underneath the table is the visual map: follow the questions ("Single edge? Chain? Glitch?") to land on the right cell before you compute. Each numbered example is tagged with the cell(s) it covers.

Cell	Case class	What makes it special	Example
A	L→H rising edge ( $t_{p L H}$ )	output charges up toward $V_{D D}$	Ex 1
B	H→L falling edge ( $t_{p H L}$ )	output discharges down toward $0$	Ex 2
C	Average $t_{p d}$ from unequal $t_{p L H}, t_{p H L}$	rise and fall differ (PMOS vs NMOS)	Ex 2
D	Zero / degenerate input	$C_{L} = 0$ , $R = 0$ , or $R \to \infty$ → limiting behaviour	Ex 3
E	Large-load limit (fan-out)	delay scales linearly with load	Ex 4
F	Chained gates — critical path & $f_{ma x}$	delays ADD; pick the longest path	Ex 5
G	Static hazard timing window	unequal path delays → glitch width	Ex 6
H	Real-world word problem	wire length → capacitance → delay	Ex 7
I	Exam twist (measure at a non-50% point)	re-derive the $ln$ factor for any threshold	Ex 8

How to read the flowchart (s04), node by node:

START (top box): ask "one gate, or a chain of gates?" — this first fork splits the whole page.
Follow the "one" arrow (left) to the blue box "ONE GATE: which edge?" From there three leaves branch out:
- the yellow "rising → A" leaf → Ex 1 (charging up),
- the pink "falling → B,C" leaf → Ex 2 (discharging down, plus the average),
- the blue "degenerate → D" leaf → Ex 3 ( $R = 0$ , $C_{L} = 0$ , or $R \to \infty$ ),
- and hanging below the rising leaf, "big load → E" → Ex 4 (fan-out scaling).
Follow the "chain" arrow (right) to the blue box "CHAIN: total or glitch?" Two leaves:
- yellow "total → F" → Ex 5 (critical path and $f_{ma x}$ ),
- pink "glitch → G" → Ex 6 (static hazard).
The bottom-right blue box "wire / threshold → H,I" is where you apply the machinery to a real-world wire (Ex 7) or an exam twist about a non-50% threshold (Ex 8).

So the rule is: walk the arrows, land on a coloured leaf, and its letter is your matrix cell.

The worked examples

Ex 1 — Rising edge $t_{p L H}$ (cell A)

Worked example Statement

A CMOS gate pulls its output up through $R = 8 k Ω$ into a load $C_{L} = 15 fF$ , supply $V_{D D} = 1.2 V$ . Find $t_{p L H}$ , the L→H delay.

Forecast: Guess — will the answer be nearer $0.1 ns$ or $10 ns$ ? (Hint: $τ$ is in the $0.1 ns$ range.)

Step 1. Time constant: $τ = R C_{L} = 8000 \times 15 \times 1 0^{- 15} = 1.2 \times 1 0^{- 10} s = 0.12 ns$ . Why this step? $τ$ sets the whole time scale; everything else is a multiple of it. On the s01 curve, this is the horizontal stretch of the yellow line.

Step 2. The output rises as $V (t) = V_{D D} (1 - e^{- t / τ})$ . We want when $V = V_{D D} /2$ — the pink dot on the s01 curve: $\frac{1}{2} = 1 - e^{- t / τ} \Rightarrow e^{- t / τ} = \frac{1}{2} \Rightarrow t = τ ln 2.$ Why this step? Delay is defined at the 50% crossing; solving the exponential for the half point gives the $ln 2$ factor. Notice $V_{D D}$ cancels — delay does not depend on supply voltage in this simple model.

Step 3. $t_{p L H} = 0.693 \times 0.12 ns = 0.0832 ns = 83.2 ps$ .

Verify: Units: $Ω \cdot F = s$ ✓. Magnitude near $0.1 ns$ as forecast ✓. Plug $t = τ ln 2$ back: $e^{- l n 2} = 0.5$ , so $V = V_{D D} (1 - 0.5) = V_{D D} /2$ ✓.

Ex 2 — Falling edge and the average $t_{p d}$ (cells B, C)

Worked example Statement

The same gate discharges through the NMOS pull-down transistor, whose ON-resistance we write $R_{n} = 4 k Ω$ (stronger than the PMOS pull-up, written $R_{p} = 8 k Ω$ , which was the plain $R$ used in Ex 1). Same $C_{L} = 15 fF$ . Find $t_{p H L}$ , then the average $t_{p d}$ .

Note on notation: where an example uses just $R$ , it means the one transistor that is switching in that example. Here two different transistors act (pull-up on the rise, pull-down on the fall), so we give them distinct names $R_{p}$ and $R_{n}$ to keep them straight.

Forecast: The pull-down resistance is half the pull-up. Will $t_{p H L}$ be bigger or smaller than $t_{p L H}$ ?

Step 1. Falling edge: output discharges toward $0$ as $V (t) = V_{D D} e^{- t / τ_{n}}$ with $τ_{n} = R_{n} C_{L}$ . Why this step? Now the cup empties: same RC physics, but the exponential decays instead of rising (the mirror image of the s01 curve).

Step 2. 50% point: $\frac{1}{2} = e^{- t / τ_{n}} \Rightarrow t = τ_{n} ln 2$ — the same $ln 2$ factor. $τ_{n} = 4000 \times 15 \times 1 0^{- 15} = 6.0 \times 1 0^{- 11} s = 0.06 ns$ . Why this step? Whether charging up or down, the half-way crossing always sits at $τ ln 2$ .

Step 3. $t_{p H L} = 0.693 \times 0.06 ns = 0.0416 ns = 41.6 ps$ . Smaller — as forecast, because $R_{n} < R_{p}$ .

Step 4. Average: $t_{p d} = \frac{t _{p L H} + t _{p H L}}{2} = \frac{83.2 + 41.6}{2} ps = 62.4 ps$ . Why this step? Datasheets quote one number; the average of the two edge delays is the convention.

Verify: $t_{p H L} < t_{p L H}$ since $R_{n} < R_{p}$ ✓. Average lies between the two ✓.

The figure shows both edges on one time axis: the blue rise ( $R_{p}$ , slower) and the pink fall ( $R_{n}$ , faster) each crossing the 50% line at their own delay.

Ex 3 — Degenerate inputs: $C_{L} = 0$ , $R = 0$ , and $R \to \infty$ (cell D)

Worked example Statement

Three thought experiments. (a) What is $t_{p d}$ if the load capacitance $C_{L} \to 0$ ? (b) What if the transistor resistance $R \to 0$ ? (c) What if $R \to \infty$ (an open circuit / dead transistor)?

Forecast: Which cases give zero delay, and which give infinite delay?

Step 1. $t_{p d} = 0.69 R C_{L}$ . Set $C_{L} = 0$ : $t_{p d} = 0.69 R \cdot 0 = 0$ . Why this step? No cup to fill → nothing takes time. An unloaded output (driving nothing) switches "instantly" in this model.

Step 2. Set $R = 0$ : $t_{p d} = 0.69 \cdot 0 \cdot C_{L} = 0$ . Why this step? A perfect (zero-resistance) wire delivers charge with no bottleneck → instant.

Step 3. Set $R \to \infty$ : $t_{p d} = 0.69 \cdot \infty \cdot C_{L} \to \infty$ . Why this step? An infinitely thin straw (a broken transistor) can never fill the cup — the output never reaches 50%, so the delay is infinite. This is the open-circuit limiting case, the exact partner of the $C_{L} \to \infty$ warning below.

Step 4. So $C_{L} = 0$ and $R = 0$ both give $t_{p d} = 0$ ; while either $R \to \infty$ or $C_{L} \to \infty$ (drive the whole chip) gives $t_{p d} \to \infty$ . That infinite-load case is the fan-out warning made mathematical.

Verify: $0.69 \times R \times 0 = 0$ and $0.69 \times 0 \times C_{L} = 0$ for any finite factor ✓. The product structure means either factor going to zero kills the delay; either going large sends it to infinity ✓.

Ex 4 — Large-load / fan-out scaling (cell E)

Worked example Statement

One gate ( $R = 5 k Ω$ ) drives $N$ identical gates, each contributing $C_{in} = 2 fF$ , plus fixed wire capacitance $C_{w} = 6 fF$ . Find $t_{p d}$ for $N = 1$ and $N = 10$ , and the extra delay per added gate.

Forecast: Delay grows with $N$ . Linearly, or faster than linearly?

Step 1. Total load: $C_{L} (N) = C_{w} + N C_{in} = 6 + 2 N$ (in fF). Why this step? Capacitances in parallel add; every driven input hangs on the same output node.

Step 2. $t_{p d} (N) = 0.69 R C_{L} = 0.69 \times 5000 \times (6 + 2 N) \times 1 0^{- 15} s$ . For $N = 1$ : $C_{L} = 8 fF \Rightarrow t_{p d} = 0.69 \times 5000 \times 8 \times 1 0^{- 15} = 2.76 \times 1 0^{- 11} s = 27.6 ps$ . For $N = 10$ : $C_{L} = 26 fF \Rightarrow t_{p d} = 0.69 \times 5000 \times 26 \times 1 0^{- 15} = 8.97 \times 1 0^{- 11} s = 89.7 ps$ . Why this step? Just substitute; the linear form $t_{p d} = 0.69 R (C_{w} + N C_{in})$ is a straight line in $N$ .

Step 3. Extra delay per gate = slope $= 0.69 R C_{in} = 0.69 \times 5000 \times 2 \times 1 0^{- 15} = 6.9 \times 1 0^{- 12} s = 6.9 ps per gate$ . Why this step? The derivative $\frac{d t _{p d}}{d N} = 0.69 R C_{in}$ is constant — hence linear growth, answering the forecast.

Verify: $27.6 + 9 \times 6.9 = 27.6 + 62.1 = 89.7 ps$ ✓ matches the $N = 10$ value directly. Linear, not super-linear ✓.

Ex 5 — Critical path and $f_{ma x}$ (cell F)

Worked example Statement

A logic block has two paths from input to output: Path 1: XOR ( $5 ns$ ) → AND ( $3 ns$ ) → OR ( $2 ns$ ). Path 2: NOT ( $1 ns$ ) → NAND ( $4 ns$ ). Find the settling time and the maximum clock frequency.

Forecast: Which path decides the answer — the one with more gates, or the one with more total time?

Step 1. Sum each path: Path 1 $= 5 + 3 + 2 = 10 ns$ ; Path 2 $= 1 + 4 = 5 ns$ . Why this step? Along a single path, each gate cannot start responding until the previous output settled — delays add.

Step 2. The output is only fully stable when the slowest path has settled: $max (10, 5) = 10 ns$ . Path 1 is the critical path. Why this step? Total-time, not gate-count, decides — the rule is always "longest total delay."

Step 3. $f_{ma x} \leq \frac{1}{t _{cr i t i c a l}} = \frac{1}{10 \times 1 0 ^{- 9} s} = 1.0 \times 1 0^{8} Hz = 100 MHz$ . Why this step? A new input can't be launched before the current one has settled everywhere.

Verify: $1/ (10 ns) = 100 MHz$ ✓. Speeding up Path 2 does nothing — it isn't critical ✓.

Recall Where to read more

The full treatment of picking the slowest path and clocking a real circuit lives in Critical path and clock frequency. In one line: the critical path is the longest sum of gate delays between two registers, and $f_{ma x} = 1/ t_{cr i t i c a l}$ — exactly what Step 3 computed.

Ex 6 — Static hazard glitch window (cell G)

Worked example Statement

Compute $Y = A \cdot \overline{A}$ . The signal $A$ reaches the AND directly, but the inverted copy $\overline{A}$ passes through a NOT gate of delay $t_{N O T} = 2.5 ns$ and then the AND itself adds $t_{A N D} = 1 ns$ to whatever it sees. Let $A$ go $0 \to 1$ at $t = 0$ . Find the glitch width seen at $Y$ .

Forecast: Ideally $Y = 0$ forever. Will the glitch last $2.5 ns$ , $1 ns$ , or $3.5 ns$ ?

Step 1. At $t = 0^{+}$ (just after $A$ switches), the direct input $A = 1$ has already arrived at the AND, but the inverted input $\overline{A}$ is still 1 until $t = 2.5 ns$ , because the NOT gate needs its own delay $t_{N O T} = 2.5 ns$ to flip. Why this step? Unequal path delays: one input to the AND changes before the other. Here " $2.5 ns$ " is specifically the NOT gate's delay $t_{N O T}$ — it is the arrival time of the inverted input, not the AND's delay.

Step 2. During the mismatch window (from when $A$ arrives until $\overline{A}$ arrives), both AND inputs are logically 1, so the AND wants to output 1. It returns to 0 once $\overline{A} \to 0$ at $t = 2.5 ns$ . Why this step? $1 \cdot 1 = 1$ briefly — a false pulse the truth table never predicts.

Step 3. The AND's own delay $t_{A N D} = 1 ns$ shifts both the rise and the fall of the glitch later by the same $1 ns$ , so the width of the glitch equals the input-arrival mismatch, $t_{N O T} = 2.5 ns$ — unchanged by $t_{A N D}$ . Why this step? A constant delay slides a pulse along the time axis but does not stretch or shrink its duration.

Verify: Glitch width $=$ difference in AND-input arrival times $= t_{N O T} - 0 = 2.5 ns$ ✓ — as forecast, the NOT delay sets the width, not the AND delay. Units: nanoseconds ✓.

The timeline figure stacks $A$ (yellow, rising at $t = 0$ ), $\overline{A}$ (blue, falling late at $t = 2.5 ns$ ) and the resulting glitch on $Y$ (pink, the shaded false pulse).

Recall Where to read more

Whether a glitch is a static or dynamic hazard, and how to remove it with a redundant term, is covered in Static and dynamic hazards. In one line: a static-1 hazard is a momentary $0$ where the output should stay $1$ (and static-0 the reverse); our $A \cdot \overline{A}$ is the classic example of a delay-caused false pulse.

Ex 7 — Real-world word problem: wire length (cell H)

Worked example Statement

A signal must travel down a $2 mm$ on-chip wire with capacitance $0.2 fF$ per micrometre ( $μ m$ ). The driving gate has $R = 3 k Ω$ . The wire also feeds a gate of input capacitance $4 fF$ . Find $t_{p d}$ . If we route a shorter $0.5 mm$ wire instead, how much delay do we save?

Forecast: Wire is $2 mm = 2000 μ m$ . Rough guess of $C_{w i r e}$ before you compute?

Step 1. Convert length: $2 mm = 2000 μ m$ . Wire cap $= 2000 \times 0.2 fF = 400 fF$ . Why this step? Capacitance is proportional to wire length; unit conversion first avoids the classic factor-of-1000 error.

Step 2. Total load $C_{L} = 400 + 4 = 404 fF$ . Why this step? Wire cap and driven-gate cap are in parallel on the same node → add.

Step 3. $t_{p d} = 0.69 \times 3000 \times 404 \times 1 0^{- 15} = 8.363 \times 1 0^{- 10} s \approx 0.836 ns$ . Why this step? Core formula; the wire dominates the load (400 vs 4 fF), showing routing matters.

Step 4. Short wire: $C_{w i r e} = 500 \times 0.2 = 100 fF$ , $C_{L} = 104 fF$ , $t_{p d} = 0.69 \times 3000 \times 104 \times 1 0^{- 15} = 2.153 \times 1 0^{- 10} s \approx 0.215 ns$ . Saving $= 0.836 - 0.215 = 0.621 ns$ .

Verify: Delay ratio $\approx 404/104 = 3.88$ ; time ratio $0.836/0.215 = 3.88$ ✓ (linear in $C_{L}$ ). Shorter wire is dramatically faster — this is why layout tools minimise wire length. See Fan-out and loading.

Ex 8 — Exam twist: measure at a non-50% threshold (cell I)

Worked example Statement

An exam asks: instead of the standard 50% point, a certain logic family declares a "1" only when the output reaches 90% of $V_{D D}$ . Derive the delay factor (the number replacing $0.69$ ), then compute the delay for $R = 5 k Ω$ , $C_{L} = 20 fF$ .

Forecast: Reaching 90% instead of 50% — bigger or smaller factor than $0.69$ ?

Step 1. General rule: to reach a fraction $x$ of $V_{D D}$ , solve $x = 1 - e^{- t / τ}$ . Why this step? The 50% case is just $x = 0.5$ ; the method re-derives the factor for any threshold.

Step 2. $e^{- t / τ} = 1 - x \Rightarrow t = τ ln (\frac{1}{1 - x})$ . For $x = 0.9$ : factor $= ln (\frac{1}{0.1}) = ln 10 \approx 2.303$ . Why this step? Higher threshold means climbing further up the exponential's flattening tail → larger factor, as forecast.

Step 3. $τ = 5000 \times 20 \times 1 0^{- 15} = 1.0 \times 1 0^{- 10} s = 0.1 ns$ . Delay $= 2.303 \times 0.1 ns = 0.2303 ns = 230.3 ps$ .

Verify: Sanity check the 50% case with the same formula: $ln (1/0.5) = ln 2 = 0.693$ ✓. And $2.303 > 0.693$ — reaching 90% takes longer than 50% ✓.

Active recall

Recall Cover the answers, then check

Which matrix cell is each? A rising edge gives $t_{p L H} = τ ln 2$ — cell? ::: A $t_{p d} = 0$ when $C_{L} = 0$ or $R = 0$ , and $t_{p d} \to \infty$ when $R \to \infty$ — cell? ::: D (degenerate) Delay per added fan-out gate $= 0.69 R C_{in}$ — cell? ::: E (large load) Longest-total-delay path sets $f_{ma x}$ — cell? ::: F (critical path) Glitch width equals the arrival-time mismatch — cell? ::: G (static hazard) To reach fraction $x$ , factor is $ln \frac{1}{1 - x}$ — cell? ::: I (non-50% twist)

Connections

Parent: Propagation delay — the core theory this page drills
RC circuits and time constant — where $τ = R C$ , the exponential, and distributed-line refinements come from
CMOS transistor structure — the source of $R$ and $C_{L}$
Fan-out and loading — Ex 4 and Ex 7 made general
Critical path and clock frequency — Ex 5 in full
Static and dynamic hazards — Ex 6 in full