Level 3 — ProductionBoolean Algebra & Logic Gates

Boolean Algebra & Logic Gates

45 minutes60 marksprintable — key stays hidden on paper

Level 3 (Production): from-scratch derivations, code-from-memory, explain-out-loud Time limit: 45 minutes Total marks: 60


Q1. Number systems & two's complement (10 marks)

(a) Convert the decimal value 45-45 into an 8-bit two's complement binary number. Show every step of the process (magnitude, invert, add 1). (4)

(b) Convert your 8-bit answer from (a) into hexadecimal and octal. (3)

(c) Perform the 8-bit two's complement addition (45)+(+19)(-45) + (+19). Show the binary addition, state the result in decimal, and explain how you check that no overflow occurred. (3)


Q2. Truth table & gate derivation from scratch (10 marks)

A safety circuit output FF over inputs A,B,CA, B, C is 1 exactly when an odd number of inputs are 1.

(a) Construct the full truth table for F(A,B,C)F(A,B,C). (4)

(b) Name the single 3-input logic function this represents and write FF as a chain of two 2-input gates of that type. (2)

(c) Explain out loud (in prose) why XOR is described as a "parity" gate, referencing your truth table. (4)


Q3. Boolean algebra — algebraic derivation (10 marks)

Starting from the expression F=ABC+ABC+ABC+ABCF = \overline{A}\,B\,C + A\,\overline{B}\,C + A\,B\,\overline{C} + A\,B\,C

simplify FF to a minimal sum-of-products form using only Boolean algebra laws (no K-map). Name the law used at each step. (10)


Q4. De Morgan & NAND universality (10 marks)

(a) State both of De Morgan's theorems in Boolean notation. (2)

(b) Using De Morgan and Boolean identities, derive from memory how to build a 2-input OR gate using only NAND gates. Give the logic expression and count the NAND gates used. (5)

(c) Explain why NAND is called a universal gate. (3)


Q5. Karnaugh map with don't-cares (12 marks)

A 4-variable function F(A,B,C,D)F(A,B,C,D) is defined by:

  • Minterms (F = 1): m(0,1,2,5,6,8,9,10,14)\sum m(0,1,2,5,6,8,9,10,14)
  • Don't-cares: d(7,11,15)d(7,11,15)

(a) Draw the 4-variable K-map, placing 1s, 0s and don't-cares correctly. (4)

(b) Derive the minimal SOP expression, clearly circling/listing the groups you use. (6)

(c) State how using the don't-care terms reduced your literal count compared to ignoring them. (2)


Q6. Quine–McCluskey + propagation delay (8 marks)

(a) For F(A,B,C)=m(0,1,2,5,6,7)F(A,B,C) = \sum m(0,1,2,5,6,7), use the Quine–McCluskey method: group minterms by 1-count, combine adjacent terms, and list the prime implicants. (5)

(b) A logic path consists of 3 gates in series with propagation delays 4 ns, 6 ns, and 3 ns. State the total worst-case propagation delay of the path and explain why series delays add. (3)

Answer keyMark scheme & solutions

Q1 (10 marks)

(a) 45-45 in 8-bit two's complement:

  • 45=00101101245 = 00101101_2 (magnitude). (1)
  • Invert bits: 1101001011010010. (1)
  • Add 1: 11010010+1=1101001111010010 + 1 = 11010011. (1)
  • Answer: 45=110100112-45 = 11010011_2. (1)

(b) From 1101001111010011:

  • Hex: group in nibbles 11010011=D3161101\,0011 = D3_{16}. (1.5)
  • Octal: group in threes from right 11010011=323811\,010\,011 = 323_8. (1.5)

(c) (45)+(+19)(-45)+(+19):

  • 45=11010011-45 = 11010011, +19=00010011+19 = 00010011. (1)
  • Sum: 11010011+00010011=1110011011010011 + 00010011 = 11100110. (1)
  • 1110011011100110 is negative; invert+1 → 00011010=2600011010 = 26, so value =26= -26 ✓ (since 45+19=26-45+19=-26). No overflow: two operands of opposite sign can never overflow (carry-in = carry-out of sign bit). (1)

Q2 (10 marks)

(a) Truth table (F = 1 for odd number of 1s): (4, ½ per row)

A B C F
0 0 0 0
0 0 1 1
0 1 0 1
0 1 1 0
1 0 0 1
1 0 1 0
1 1 0 0
1 1 1 1

(b) This is the 3-input XOR (parity) function. F=(AB)CF = (A \oplus B) \oplus C. (2)

(c) XOR outputs 1 iff its inputs differ; cascading XORs accumulates the parity. Looking at the table, F=1 exactly on rows where the count of 1s is odd (1 or 3). Each XOR effectively counts a "toggle," so the final output reports whether the total number of set bits is odd — the definition of odd parity. (4) (2 for correct link to odd-count rows, 2 for coherent parity explanation)


Q3 (10 marks)

F=ABC+ABC+ABC+ABCF = \overline{A}BC + A\overline{B}C + AB\overline{C} + ABC

  • Factor last two terms: ABC+ABC=AB(C+C)=AB1=ABAB\overline{C} + ABC = AB(\overline{C}+C) = AB\cdot 1 = ABDistributive + Complement + Identity. (3)
  • Now F=ABC+ABC+ABF = \overline{A}BC + A\overline{B}C + AB.
  • Group ABC+ABC\overline{A}BC + ABC'... instead combine ABC\overline{A}BC with ABCABC (re-add ABCABC using idempotent AB=AB+ABCAB = AB + ABC): ABC+ABC=BC(A+A)=BCABC + \overline{A}BC = BC(A+\overline{A}) = BCIdempotent / Distributive / Complement. (3)
  • Similarly ABC+ABC=AC(B+B)=ACA\overline{B}C + ABC = AC(B+\overline{B}) = AC. (2)
  • So F=AB+BC+ACF = AB + BC + AC (consensus form, minimal). (2)

Final: F=AB+AC+BCF = AB + AC + BC.


Q4 (10 marks)

(a) De Morgan's theorems: (2) A+B=AB,AB=A+B\overline{A+B} = \overline{A}\cdot\overline{B}, \qquad \overline{A\cdot B} = \overline{A}+\overline{B}

(b) OR from NAND: (5)

  • A+B=A+B=ABA + B = \overline{\overline{A+B}} = \overline{\overline{A}\cdot\overline{B}} (De Morgan). (2)
  • A\overline{A} = A NANDed with itself = AA\overline{A\cdot A}; similarly B\overline{B}. (1)
  • AB\overline{\overline{A}\cdot\overline{B}} = NAND of A\overline{A} and B\overline{B}. (1)
  • Total NAND gates: 2 (inverters) + 1 (final NAND) = 3 NAND gates. (1)

(c) NAND is universal because any Boolean function can be realised using NAND gates alone — NOT, AND, and OR can all be constructed from NAND, and {AND, OR, NOT} is a functionally complete set. (3)


Q5 (12 marks)

(a) K-map (rows AB, cols CD in Gray order 00,01,11,10): (4)

AB\CD 00 01 11 10
00 1(0) 1(1) -(3?) 1(2)
01 0(4) 1(5) d(7) 1(6)
11 0(12) 0(13) d(15) 1(14)
10 1(8) 1(9) d(11) 1(10)

Minterms 0,1,2,5,6,8,9,10,14 = 1; 7,11,15 = d; rest = 0. (m3 = 0.)

(b) Minimal SOP groups: (6)

  • BC\overline{B}\,\overline{C} — cells 0,1,8,9 (AB=00/10, CD=00/01). (2)
  • CDC\overline{D} — cells 2,6,10,14 (all rows, CD=10). (2)
  • BCDB\overline{C}D or use d(7): group 5,7 with... choose AD\overline{A}\,D? Cover m5. Group 1,5 = ACD\overline{A}\,\overline{C}D; using d7: 5,7 = ABD\overline{A}BD. Simplest cover of m5: ACD\overline{A}\,\overline{C}\,D (cells 1,5) or with don't cares group 5,7,13?,15 — 15 is d, 13=0. Take 5,7,15,13 invalid (13=0). Use 5,7 + d15,d... Group BDBD needs 5,7,13,15 but 13=0. So cover m5 via AD\overline{A}D (cells 1,5,3d,7d) valid since 3=? m3=0, not d. So AD\overline{A}D covers 1,3,5,7 but 3=0 → invalid. Use ACD\overline{A}\,\overline{C}D (1,5). (2)

Minimal SOP: F=BC+CD+ACDF = \overline{B}\,\overline{C} + C\overline{D} + \overline{A}\,\overline{C}D.

(c) Don't-cares (7,11,15) allowed larger groupings (extending prime implicants across those cells), reducing the total literal count versus treating them as 0. Accept any reasoned statement of literal saving. (2)


Q6 (8 marks)

(a) Quine–McCluskey for m(0,1,2,5,6,7)\sum m(0,1,2,5,6,7): (5)

Binary minterms grouped by 1-count:

  • Group0: 0 = 000
  • Group1: 1 = 001, 2 = 010
  • Group2: 5 = 101, 6 = 110
  • Group3: 7 = 111

Combine adjacent (differ in 1 bit):

  • 0,1 = 00- ; 0,2 = 0-0
  • 1,5 = -01 ; 2,6 = -10
  • 5,7 = 1-1 ; 6,7 = 11-

Second combination:

  • (none combine further into size-4 — check pairs share dash & differ 1 bit: no valid 4-cell groups).

Prime implicants: AB\overline{A}\,\overline{B} (00-), AC\overline{A}\,\overline{C} (0-0), BC\overline{B}\,C (-01), BCB\overline{C} (-10), ACAC (1-1), ABAB (11-). (5)

(Minimal cover e.g. F=AB+BC+BC+ABF = \overline{A}\,\overline{B} + \overline{B}C + B\overline{C} + AB or similar — full accept for correct PI list.)

(b) Total worst-case delay =4+6+3=13= 4 + 6 + 3 = 13 ns. Series delays add because each gate can only begin switching after its input (the previous gate's output) has settled; the signal must propagate through each stage sequentially. (3)

[
  {"claim":"45 magnitude then two's complement gives 11010011","code":"val=45\nbits=format(val,'08b')\ninv=''.join('1' if b=='0' else '0' for b in bits)\ntc=format(int(inv,2)+1,'08b')\nresult=(tc=='11010011')"},
  {"claim":"11010011 base2 equals D3 hex and 323 octal","code":"n=int('11010011',2)\nresult=(format(n,'X')=='D3' and format(n,'o')=='323')"},
  {"claim":"-45 + 19 = -26 in 8-bit two's complement (11100110)","code":"a=(-45)&0xFF\nb=19&0xFF\ns=(a+b)&0xFF\nsigned=s-256 if s>=128 else s\nresult=(s==0b11100110 and signed==-26)"},
  {"claim":"F=A'BC+AB'C+ABC'+ABC simplifies to AB+AC+BC","code":"A,B,C=symbols('A B C')\nfrom sympy.logic.boolalg import Or,And,Not,simplify_logic\nF=Or(And(Not(A),B,C),And(A,Not(B),C),And(A,B,Not(C)),And(A,B,C))\nG=Or(And(A,B),And(A,C),And(B,C))\nresult=(simplify_logic(F)==simplify_logic(G))"},
  {"claim":"total series propagation delay 4+6+3 = 13 ns","code":"result=(4+6+3==13)"}
]