Logic gate propagation delay — Hinglish notes

3.1.15 · Hardware › Boolean Algebra & Logic Gates

Propagation delay KYA hai?

50% KYO? Kyunki "logic threshold" (woh voltage jis par agla gate decide karta hai ki 1 hai ya 0) roughly halfway par hota hai. 50% par measure karna ek consistent, technology-independent reference point hai.

Note karo iska fark transition (rise/fall) time se: woh ek signal ke 10% aur 90% points ke beech measure hota hai aur describe karta hai ki edge kitni sharp hai — yeh ek alag quantity hai.

Delay KYUN exist karta hai? (First principles se derivation)

Ek CMOS gate output ek load capacitance $C_{L}$ drive karta hai (wire capacitance + un gates ki input capacitances jo isse feed hoti hain). Jab output switch karta hai, toh ek transistor ko us capacitor pe ya us se charge move karna padta hai apne channel resistance $R$ ke through.

Switching transistor ko ek resistor $R$ manke model karo jo capacitor $C_{L}$ ko supply $V_{D D}$ se charge kar raha hai. KCL se, cap ko charge karne wala current resistor ke through current ke barabar hai:

$C_{L} \frac{d V}{d t} = \frac{V _{D D} - V}{R}$

Yeh step kyun? Same current $R$ se flow karta hai aur $C_{L}$ mein jaata hai (series path), aur ek capacitor ka current definition se $C d V / d t$ hota hai.

Variables alag karo aur $V = 0$ se integrate karo:

$\frac{d V}{V _{D D} - V} = \frac{d t}{R C _{L}} \Rightarrow - ln (V_{D D} - V) = \frac{t}{R C _{L}} + k$

$V (0) = 0$ apply karne se $k = - ln V_{D D}$ milta hai, isliye:

$V (t) = V_{D D} (1 - e^{- t / R C_{L}})$

Yeh step kyun? Yeh standard exponential charging curve hai — output jump nahi karta; yeh time constant $τ = R C_{L}$ ke saath $V_{D D}$ tak dheere-dheere ease karta hai.

Ab $t_{p L H}$ nikalo: 50% point $V = V_{D D} /2$ tak pahunchne ka time:

$\frac{V _{D D}}{2} = V_{D D} (1 - e^{- t / R C_{L}}) \Rightarrow e^{- t / R C_{L}} = \frac{1}{2} \Rightarrow t = R C_{L} ln 2$

Consequences jo ab tum predict kar sakte ho (Forecast-then-Verify):

Zyada gates drive karo → bada $C_{L}$ → zyada delay. (Fan-out time ki cost lagata hai.)
Bada/zyada strong transistor use karo → chhota $R$ → kam delay (lekin pichle gate ke liye badi input cap!).
Lambe wires → zyada $C_{L}$ → zyada delay.

Delays ek path mein ADD hote hain

Worked examples

Common mistakes

Active recall

Recall Pehle khud try karo, phir reveal karo

$t_{p d}$ define karo aur use kiye gaye reference points batao.
RC charging equation se $t_{p d} = 0.69 R C_{L}$ derive karo.
Fan-out delay kyun badhata hai?
Static hazard glitch kya cause karta hai?

Ek logic gate ki propagation delay kya hoti hai?

Woh time jab input apne voltage swing ka 50% cross kare tab se jab output 50% cross kare, us change ke response mein.

Delay 50% point par kyun measure ki jaati hai?

Kyunki logic threshold (jahan agla gate 0 vs 1 decide karta hai) ~halfway hoti hai, jo ek consistent technology-independent reference deti hai.

t_pLH aur t_pHL kya hain?

Output ke Low→High aur High→Low jaane ke delays respectively.

Delay formula derive karo: output rise ko kaunsi equation govern karti hai?

C_L dV/dt = (V_DD − V)/R, jisse V(t)=V_DD(1−e^(−t/RC_L)) milta hai.

R aur C_L ke terms mein propagation delay kya hai?

t_pd ≈ 0.69·R·C_L (kyunki ln2 ≈ 0.693).

Fan-out ke saath delay kyun badhti hai?

Zyada gates drive karna = bada load capacitance C_L, aur delay ∝ C_L.

Gates ki chain mein delays kaise combine hoti hain?

Woh ek path ke along ADD hoti hain; sabse lamba (critical) path max clock frequency f_max = 1/t_critical set karta hai.

Propagation delay aur rise time mein fark?

Propagation delay do signals ke beech 50%(in)→50%(out) hai; rise/fall time EK signal ka 10%→90% hai (edge sharpness).

Static hazard (glitch) kya hota hai?

Ek brief false output pulse jo unequal path delays ki wajah se ek gate ke inputs alag times par arrive karte hain.

Kya driving transistor ko bada karna hamesha circuit ko fast karta hai?

Nahi — chhota R help karta hai, lekin uski badi input capacitance pichle stage ko slow karti hai; yeh ek trade-off hai.

Recall Feynman: ek 12-saal ke bachche ko explain karo

Socho ek cup ko paani se ek patli straw ke zariye bharna. Chahe tum instantly decide karo ki use bharna hai, paani phir bhi halfway line tak pahunchne mein ek moment leta hai. Ek logic gate aisa hi hai: "paani" electric charge hai, "cup" ek tiny capacitor hai, aur "straw" transistor ki resistance hai. Gate jawab turant jaanta hai, lekin voltage ko actually uthane mein thoda time lagta hai jahan agla gate use padh sake. Kai cups aur straws ko chain karo, aur wait karne ke times add hote jaate hain — isliye fast computers zyada mehnat karte hain in straws ko mota aur cups ko chhota rakhne ke liye.

Connections

Boolean Algebra & Logic Gates — logic layer jiske upar yeh timing layer baithti hai
CMOS transistor structure — $R$ aur $C_{L}$ real MOSFETs se aate hain
RC circuits and time constant — $0.69 R C$ result ka source
Static and dynamic hazards — delay mismatch se caused glitches
Critical path and clock frequency — kaise $t_{p d}$ $f_{ma x}$ ko limit karta hai
Fan-out and loading — kyun kai gates drive karna slow hota hai