Critical path identification

WHAT is a critical path?

WHAT it is NOT: it is not the physically longest wire, and not the path with the most gates. A path with 3 slow gates can beat a path with 10 fast ones. It's about accumulated delay, not gate count.

WHY does it exist / WHY do we care?

Every register captures data on a clock edge. For data launched on edge $N$ to be safely captured on edge $N+1$ , it must arrive before the setup deadline. If even one path is too slow, that capture fails → wrong bits latched → functional failure.

HOW: deriving the timing constraint from scratch

Let's build the setup constraint from the physics of a flip-flop pair, no memorizing.

Timeline of one data hop (launch FF → logic → capture FF):

Clock edge arrives at launch FF. After a delay == $t_{cq}$ == (clock-to-Q), data appears at Q.
Data ripples through combinational logic, taking == $t_{logic}$ == (this is the path delay we sum up).
Data arrives at the capture FF's D input. It must be stable before the next clock edge by the setup time == $t_{su}$ ==.

The next clock edge comes one period $T$ later. So the available time is $T$ ; the used time is $t_{cq} + t_{logic} + t_{su}$ .

WHY this step (the inequality): for correct capture, used time ≤ available time:

$t_{cq} + t_{logic} + t_{su} \le T$

Solving for the fastest allowed clock (worst path dominates):

Refinement — clock skew. If the capture clock arrives $t_{skew}$ later than the launch clock, the deadline is pushed out, giving you more time:

$t_{cq} + t_{logic} + t_{su} \le T + t_{skew}$

HOW an EDA / STA tool finds it (the algorithm)

Static Timing Analysis (STA) doesn't simulate vectors — it does graph math:

Model the netlist as a Directed Acyclic Graph (nodes = gate pins, edges = delays).
Break combinational feedback at flip-flops (registers are the graph "cut points").
Compute Arrival Time (AT) at every node = max over incoming paths of (source AT + edge delay). This is a forward topological pass.
Compute Required Arrival Time (RAT) backward from endpoints using $T$ , $t_{su}$ .
Slack = RAT − AT at each node. The endpoint with the worst slack terminates the critical path; trace back along max-delay predecessors to reconstruct it.

Worked examples

Forecast-then-Verify

Recall Forecast before reading the answer

Q: A path has 20 tiny gates each 0.1 ns; another has 2 big gates each 3 ns. $t_{cq}=t_{su}=0.5$ ns. Which is critical and what is $f_{\max}$ ? Verify: Path 1 = $2$ ns, Path 2 = $6$ ns → Path 2 critical. $T_{\min}=0.5+6+0.5=7$ ns → $f_{\max}\approx 142.9$ MHz. Gate count fooled no one who summed delays.

Common mistakes (Steel-man + fix)

Recall Feynman: explain to a 12-year-old

Imagine a class doing a bucket-brigade to fill a tank, one splash per whistle. Everyone must pass their bucket before the next whistle. The slowest kid decides how long you must wait between whistles — if you whistle too fast, that one slow kid drops the bucket and water spills (wrong answer). Finding the "slowest kid" chain in a circuit is finding the critical path. To go faster, either train the slow kid (faster gates) or split their long run into two (add a register).

Active-recall flashcards

What is the critical path in a synchronous circuit?

The register-to-register combinational path with the largest total propagation delay (least timing slack); it sets the max clock frequency.

Write the setup timing inequality.

t_{cq} + t_{logic} + t_{su} \le T + t_{skew}

Define setup slack.

\text{slack} = T + t_{skew} - (t_{cq} + t_{logic} + t_{su})

; the critical path has the minimum slack.

Is the critical path the one with the most gates?

No — it's the one with the greatest summed delay; gate count is irrelevant.

At a multi-input gate, arrival time = ?

max(input arrival times) + gate delay, because the output waits for the last input.

How does STA find the critical path?

Model netlist as a DAG, forward pass for arrival times (using max), backward pass for required times, slack = RAT − AT, trace worst-slack endpoint.

One technique to shorten a critical path.

Pipelining — insert a register to split one long path into shorter stages (adds latency, raises

f_{max}

Does capture-clock skew help or hurt setup timing?

Positive capture skew relaxes setup (

+t_{skew}

gives more time), but hurts hold timing.

t_{cq}=1

t_{logic}=6

t_{su}=1

ns, no skew, find

f_{max}

T_{min}=8

ns →

f_{max}=125

MHz.

Slack vs delay?

Delay = time used along a path; slack = required time − arrival time (spare margin). Negative slack = violation.

Connections

Setup and Hold Time — the constraints whose violation the critical path predicts
Static Timing Analysis (STA) — the tool/algorithm that reports critical paths
Clock Skew and Jitter — modifies the effective deadline
Pipelining — primary technique to break a long critical path
Propagation Delay and Gate Sizing — the $t_{logic}$ ingredients
Maximum Clock Frequency — the number the critical path ultimately sets
Synchronous Design Flow — where critical-path checking lives in the flow

Concept Map

Hinglish (regional understanding)

Intuition Hinglish mein samjho

Dekho, koi bhi synchronous circuit utni hi fast chal sakti hai jitni uski sabse slow path allow kare. Do flip-flops ke beech mein jo combinational logic hoti hai, uske through data ko ek clock edge se launch hoke agle clock edge tak pahunchna padta hai. Jis path mein delay sabse zyada hai — usko critical path kehte hain. Ye path akela hi decide karta hai ki poori chip kitni fast clock pe chalegi.

Formula khud derive karo, ratto mat: clock edge aata hai, flip-flop ko output dene mein $t_{cq}$ lagta hai, phir logic mein $t_{logic}$ , aur capture flip-flop ke setup ke liye data $t_{su}$ pehle ready hona chahiye. Sab jodo, aur wo period $T$ ke andar fit hona chahiye: $t_{cq}+t_{logic}+t_{su}\le T$ . Bas yahi setup constraint hai. Critical path wahi hai jiska slack (bacha hua time) sabse kam hai.

Sabse bada trap: log sochte hain jis path mein zyada gates hain wahi slow hogi. Galat! Delay gate count se nahi, actual delay sum se decide hoti hai. 5 fast gates (5 ns) beat kar sakte hain 3 slow gates (6 ns) ko. Isliye hamesha delays add karo, gate ginna band karo.

Agar critical path bahut slow hai to do options: fast gates lagao, ya pipelining karo — beech mein ek register daal do taaki ek lambi path do choti paths mein tut jaye. Har fix ke baad STA dobara chalao, kyunki purani second-slowest path ab nayi critical ban jaati hai. Yahi timing closure ka asli khel hai!

WHAT is a critical path?

WHY does it exist / WHY do we care?

HOW: deriving the timing constraint from scratch

HOW an EDA / STA tool finds it (the algorithm)

Worked examples

Forecast-then-Verify

Common mistakes (Steel-man + fix)

Active-recall flashcards

Connections

Concept Map

Hinglish (regional understanding)

Go deeper — visual, from zero

Test yourself — HDL & Digital Design Flow

Connections