Foundations — Critical path identification

Before you can find a critical path, you must be fluent in the words and symbols the parent note throws at you: flip-flop, clock edge, propagation delay, $t_{cq}$, $t_{logic}$, $t_{su}$, $t_h$, $T$, skew, slack, arrival time, DAG. We build each one from a picture. Nothing is assumed.

1. The clock — the drumbeat everything obeys

Look at the top of the first figure. The blue trace is the clock. Two rising edges are marked; the horizontal gap between them is exactly $T$. Everything in this chapter is a race to finish work inside one such gap.

2. The flip-flop — the memory cell that "photographs" data

Think of it as a camera: $D$ is the scene, the clock edge is the shutter click, $Q$ is the developed photo that stays fixed on the wall until you click again.

The parent note names two roles a flip-flop can play:

In the second figure, the left box is the launch FF, the right box is the capture FF, and the cloud between them is the logic the data must cross. This launch→logic→capture trio is the unit of everything — a single "hop".

3. Propagation delay — nothing in a chip is instant

Picture a domino: you push the first one now, but the last one falls a moment later. That lag is delay. Every gate in the logic cloud adds its own lag.

Two flavours of delay: max (propagation) and min (contamination)

A gate does not have one delay — it has a slowest and a fastest. You need both to do timing correctly.

4. The three timing numbers of a flip-flop: $t_{cq}$, $t_{su}$, $t_h$

A flip-flop is not a perfect instant camera. It has three tiny timing quirks the parent note leans on constantly.

Look at the third figure: on the clock edge it shows the "no-change" window opening $t_{su}$ before the edge and closing $t_h$ after it, plus the $t_{cq}$ lag before $Q$ moves.

5. Putting the numbers on the timeline (the SETUP constraint)

Now the parent's key inequality stops being magic. Trace one hop against the clock period, exactly as drawn in the fourth figure. Because we ask "did data arrive in time?", we use the slowest logic delay $t_{logic}^{\max }$.

1. Rising edge at the launch FF (start of the race).
2. Wait $t_{cq}$ — new data leaves $Q$.
3. Wait $t_{logic}^{\max }$ — data crawls across the logic cloud along its slowest path (this is the summed max path delay defined in §3).
4. Data must now be quiet for $t_{su}$ before the next edge, which arrives $T$ later.

That is literally the picture read left to right. The parent's whole page is built on this one line — see Static Timing Analysis (STA) for how a tool checks it on millions of paths, and Maximum Clock Frequency for turning $T$ into $f_{\max }=1/T$.

6. The HOLD constraint — the "too early" danger

Setup guards against data being too late. There is an opposite failure: new data racing through so fast that it reaches the capture FF's $D$ before that same edge has finished storing the old value. That corrupts the capture — a hold violation.

The key insight: setup compares against the next edge ($T$ later), but hold compares against the same edge — both flip-flops react to edge $N$. There is no $T$ in a hold check.

Trace the fifth figure: at edge $N$ the launch FF fires; the new value reaches the capture $D$ after $t_{cq}^{\min }+t_{logic}^{\min }$. For a safe capture, the old data must still be held for $t_h$ after the edge — so the new data must arrive no earlier than $t_h$:

7. Skew — when the two clocks don't click together

If the capture clock is late (positive skew), the capture deadline moves later — you gain time for setup, but you lose margin for hold (the capture FF is still holding old data even longer relative to the launch FF's early launch):

The $+t_{skew}$ sits on the "available" side because a late capture edge is extra breathing room for setup. Compare the hold formula in §6, where $+t_{skew}$ sits on the demand side — that is exactly the "sign flip" the parent warns about: the same positive skew helps setup and hurts hold.

8. Arrival time, required time, and slack

STA doesn't watch data flow — it does bookkeeping with three quantities per wire node.

9. The DAG — the map STA walks on

Why acyclic matters: to add up delays along paths you must have a clear "start" and "end". A loop would have no finish line. Flip-flops provide the cuts, so every hop is a tidy directed path with a launch and a capture end. The forward "max" pass computes AT; the backward "min" pass computes RAT.

Prerequisite map

Equipment checklist

Test yourself — cover the right side and answer each before revealing.