Worked examples — Critical path identification

This page is a case-by-case drill for the parent note Critical path identification. The parent showed you what a critical path is and why it sets the clock. Here we hit every kind of situation a problem can throw at you: normal cases, ties, zero delays, negative slack, hostile skew, hold-time twists, and a real-world word problem. Nothing new is assumed — every symbol is re-introduced the first time it appears.

A unit sanity note we will lean on: $1\text{ ns}=10^{-9}\text{ s}$, so a period of $T$ ns gives $f=\frac{1}{T\times 10^{-9}\text{ s}}=\frac{1000}{T}\text{ MHz}$. Memorise the shortcut: frequency in MHz = 1000 ÷ (period in ns).

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The scenario matrix

Every timing problem you will meet falls into one of these cells. The worked examples below are each tagged with the cell they cover, so together they fill the whole grid.

#	Cell class	What makes it tricky	Example
C1	Two competing paths, no skew	pick slower by summed delay, not gate count	Ex 1
C2	Tie in delay, differ in gate count	equal-delay paths — both critical	Ex 2
C3	Positive skew (helpful)	capture clock late ⇒ more time	Ex 3
C4	Negative skew (harmful)	capture clock early ⇒ deadline pulled in	Ex 4
C5	Negative slack (violation)	path fails; must fix	Ex 5
C6	Degenerate: $t_{logic}=0$	wire-only path, still has $t_{cq}+t_{su}$ floor	Ex 6
C7	Multi-input gate (arrival = max)	last input wins at a merge	Ex 7
C8	Hold-time twist (fast path)	shortest path, opposite inequality	Ex 8
C9	Real-world word problem	translate English → the five symbols	Ex 9
C10	Exam twist: fix then re-check	second path becomes new critical	Ex 10

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Example 1 — two competing paths, no skew (C1)

Forecast: Path B has more gates — does that make it critical? Guess before reading.

1. Sum each path's delay. Path A $=3+1+3+1=8$ ns. Path B $=6\times 1.2=7.2$ ns. Why this step? The critical path is decided by accumulated delay, never by gate count. Look at the figure: Path A's total bar is longer even though it has fewer segments.
2. Take the larger. $t_{logic}^{\max }=8$ ns (Path A). Path B loses despite two extra gates. Why this step? The clock must wait for the slowest runner; the fast path just idles.
3. Plug into $T_{\min }$. $T_{\min }=t_{cq}+t_{logic}^{\max }+t_{su}=0.8+8+0.7=9.5$ ns. Why this step? One full data hop must fit in one period.
4. Convert to frequency. $f_{\max }=1000/9.5\approx 105.3$ MHz.

Verify: Path A (8) > Path B (7.2), so more gates did not win — matches the "count is irrelevant" rule. Units: $9.5$ ns period → $1000/9.5\approx 105.3$ MHz. ✓

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Example 2 — a tie in delay (C2)

Forecast: Can two paths be critical at once?

1. Sum both. P $=6$ ns, Q $=6$ ns. They tie. Why this step? Delay, not count, is the tiebreaker — and here the delays are equal.
2. Both are critical. Any path with the maximum delay is a critical path; a design can have several. Why this step? The definition says "largest total delay" — ties share the crown, and fixing only one leaves the other still limiting you.
3. Frequency floor. $T_{\min }=1+6+1=8$ ns, $f_{\max }=1000/8=125$ MHz.

Verify: $6=6$, so both bind. $T_{\min }=8$ ns → $125$ MHz. ✓ (Lesson: to speed up, you'd have to shorten both paths.)

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Example 3 — positive skew helps (C3)

Forecast: Does making the capture clock late help or hurt?

1. Time spent. $t_{cq}+t_{logic}+t_{su}=0.5+5+0.5=6$ ns. Why this step? This is the used portion of the ruler.
2. Time available. $T+t_{skew}=6+0.5=6.5$ ns. Why this step? A later capture edge pushes the deadline outward — the figure shows the green deadline sliding right by $0.5$ ns, giving breathing room.
3. Slack. $\text{slack}=6.5-6=+0.5$ ns.

Verify: Positive skew added exactly its value to the slack. Without skew, slack would be $6-6=0$ (right on the edge); the $+0.5$ pushed it to $+0.5$ ns. Helpful, as forecast. ✓

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Example 4 — negative skew hurts (C4)

Forecast: How does an early deadline change the sign of the slack?

1. Time spent (unchanged): $0.5+5+0.5=6$ ns.
2. Time available: $T+t_{skew}=6+(-0.5)=5.5$ ns. Why this step? Negative skew means the capture edge comes before the nominal one — the deadline slides left, stealing time.
3. Slack: $5.5-6=-0.5$ ns. Violation.

Verify: Same numbers as Ex 3 but skew flipped sign flipped the slack from $+0.5$ to $-0.5$ — a symmetric $1$ ns swing. ✓ Confirms the parent's "track which clock the skew shifts."

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Example 5 — negative slack, a real violation (C5)

Forecast: The logic alone is bigger than the whole period — can this ever pass?

1. Slack. $\text{slack}=(8+0)-(1+9+1)=8-11=-3$ ns. Why this step? Negative means the data arrives $3$ ns after the deadline — the bit is still moving when it's supposed to be still.
2. Interpret. A $-3$ ns violation. You must recover $3$ ns.
3. Two fixes. (a) Slow the clock: minimum safe period $T_{\min }=1+9+1=11$ ns → $f_{\max }=1000/11\approx 90.9$ MHz. (b) Shorten logic by $\ge 3$ ns (resize gates / pipeline).

Verify: $-3$ ns < 0 ⇒ fails. Relaxing to $T=11$ ns gives slack $11-11=0$, exactly on the boundary. $1000/11\approx 90.9$ MHz. ✓

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Example 6 — degenerate path, zero logic (C6)

Forecast: With zero logic, can the clock go infinitely fast?

1. Plug $t_{logic}=0$. $T_{\min }=t_{cq}+0+t_{su}=0.6+0+0.4=1.0$ ns. Why this step? Even a bare wire cannot escape the flip-flop's own overheads — the clock-to-Q push-out and the setup catch still cost time.
2. Frequency. $f_{\max }=1000/1.0=1000$ MHz $=1$ GHz. Why this step? This is the hard ceiling for this FF pair; no logic path between them can beat it.

Verify: Setting $t_{logic}=0$ leaves the irreducible floor $t_{cq}+t_{su}=1.0$ ns. Not infinite — matches the physics. $1000/1.0=1000$ MHz. ✓

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Example 7 — multi-input gate, arrival = max (C7)

Forecast: Do we add the three input times, or pick one?

1. Take the max input arrival. $\max (4,7,5)=7$ ns. Why this step? An AND's output cannot settle until its slowest input has arrived — the figure shows the output waiting on the plum ($7$ ns) input while the others sit idle.
2. Add the gate delay. Output valid at $7+1=8$ ns. Why this step? Once the last input is in, the gate itself still takes $1$ ns to react.
3. Critical predecessor. The $7$ ns input is on the critical path through this gate; trace back along it.

Verify: We used $\max$, not sum ($4+7+5=16$ would be nonsense — inputs travel in parallel, not in series). $\max =7$, $+1=8$ ns. ✓ This is exactly the parent's "arrival = max(inputs) + gate delay."

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Example 8 — the hold-time twist, shortest path (C8)

Forecast: The setup formula rewarded a late capture clock. Does that same lateness hurt hold?

1. Left side (data arrival). $t_{cq}+t_{logic}=0.3+0.2=0.5$ ns. Why this step? This is how fast new data reaches the capture FF after the same edge.
2. Right side (hold requirement). $t_h+t_{skew}=0.6+0.3=0.9$ ns. Why this step? Positive skew that helped setup now hurts hold — the late capture edge means old data must survive longer.
3. Compare. $0.5\ge 0.9$? No. Hold violation (hold slack $=0.5-0.9=-0.4$ ns).

Verify: The very skew that gave $+0.5$ ns of setup room in Ex 3 costs us here — $0.5<0.9$ fails. Hold slack $=-0.4$ ns. ✓ Confirms the parent's mistake-note: skew's sign effect flips between setup and hold.

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Example 9 — real-world word problem (C9)

Forecast: First translate every phrase into one of our five symbols before computing.

1. Translate. ($1$ ns $=1000$ ps.)
   • "launches $250$ ps after the edge" → $t_{cq}=0.25$ ns.
   • adder + mux + comparator, in series → $t_{logic}=1.4+0.35+0.9=2.65$ ns.
   • "stable $200$ ps ahead" → $t_{su}=0.20$ ns.
   • "capture edge $150$ ps later" → $t_{skew}=+0.15$ ns. Why this step? Every timing word maps to exactly one symbol; series gates add.
2. Minimum period (skew helps setup, so subtract it): $T_{\min }=t_{cq}+t_{logic}+t_{su}-t_{skew}=0.25+2.65+0.20-0.15=2.95$ ns. Why this step? This is the setup formula rearranged; the late capture clock buys back $0.15$ ns.
3. Frequency. $f_{\max }=1000/2.95\approx 339.0$ MHz.

Verify: Sum $0.25+2.65+0.20=3.10$ ns of used time, minus $0.15$ ns skew relief $=2.95$ ns. $1000/2.95\approx 339.0$ MHz. ✓ Units consistent (all ns → MHz).

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Example 10 — exam twist: fix, then the next path bites (C10)

Forecast: After you fix the worst path, will $8$ ns finally be met?

1. (a) Critical now. $\max (12,9.5)=12$ ns → Path X critical. Its stage need is $0.5+12+0.5=13$ ns > 8 ns: fails badly. Why this step? Worst summed delay wins.
2. (b) Pipeline X. Split X into two $6$ ns halves; each new stage needs $0.5+6+0.5=7$ ns ≤ 8 ns. ✓ But Path Y is untouched: it needs $0.5+9.5+0.5=10.5$ ns > 8 ns. Still fails. Why this step? Fixing X promoted Y to the new critical path — the classic "second-slowest becomes critical" trap. Re-run STA after every fix.
3. (c) New $f_{\max }$. The block's floor is now Path Y: $T_{\min }=10.5$ ns → $f_{\max }=1000/10.5\approx 95.2$ MHz. To reach $8$ ns you must also shorten/pipeline Y.

Verify: After pipelining X, the halves ($7$ ns) pass but Y ($10.5$ ns) does not — so the block does not meet $8$ ns. $1000/10.5\approx 95.2$ MHz. ✓ Matches the parent's "speed up the critical path and you're done" mistake.

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Recall Which cell was hardest for you?

Skew sign — setup vs hold ::: Late capture clock (positive skew) helps setup (adds to available time) but hurts hold (old data must survive longer). Ex 3 vs Ex 8. Why "most gates" fools people ::: Delay is summed, not counted; a few slow gates beat many fast ones. Ex 1, Ex 2. The irreducible speed floor ::: Even with $t_{logic}=0$, $T_{\min }=t_{cq}+t_{su}$. Ex 6. Multi-input merge rule ::: Output arrival = max(input arrivals) + gate delay, never the sum. Ex 7.

Related vault topics

• Parent: Critical path identification · Hinglish: 3.5.10 Critical path identification (Hinglish)
• Foundations: Setup and Hold Time · Propagation Delay and Gate Sizing
• The tool that automates all of this: Static Timing Analysis (STA)
• Skew's double-edged role: Clock Skew and Jitter
• Speed limits and fixes: Maximum Clock Frequency · Pipelining · Synchronous Design Flow