Critical path identification — Hinglish notes

3.5.10 · Hardware › HDL & Digital Design Flow

WHAT hai critical path?

WHAT nahi hai yeh: yeh physically sabse lambi wire nahi hai, aur sabse zyada gates wali path bhi nahi hai. 3 slow gates wali path 10 fast gates wali path ko piche chhod sakti hai. Baat accumulated delay ki hai, gate count ki nahi.

WHY exist karta hai / WHY care karein?

Har register ek clock edge par data capture karta hai. Edge $N$ par launch hue data ko edge $N + 1$ par safely capture hone ke liye, woh setup deadline se pehle pahunchna chahiye. Agar ek bhi path zyada slow hai, toh woh capture fail hoga → galat bits latch honge → functional failure.

HOW: timing constraint ko scratch se derive karna

Chalte hain setup constraint ko flip-flop pair ki physics se build karein, kuch memorize karne ki zaroorat nahi.

Ek data hop ki timeline (launch FF → logic → capture FF):

Clock edge launch FF par pahunchti hai. == $t_{c q}$ == (clock-to-Q) delay ke baad, data Q par appear hota hai.
Data combinational logic se guzarta hai, == $t_{l o g i c}$ == lete hue (yahi woh path delay hai jo hum sum karte hain).
Data capture FF ke D input par pahunchta hai. Yeh agle clock edge se pehle stable hona chahiye, setup time == $t_{s u}$ == se.

Agla clock edge ek period $T$ baad aata hai. Toh available time hai $T$ ; used time hai $t_{c q} + t_{l o g i c} + t_{s u}$ .

WHY yeh step (inequality): sahi capture ke liye, used time ≤ available time:

$t_{c q} + t_{l o g i c} + t_{s u} \leq T$

Sabse fast allowed clock ke liye solve karein (worst path dominate karta hai):

Refinement — clock skew. Agar capture clock $t_{s k e w}$ baad mein pahunche launch clock se, toh deadline aage push ho jaati hai, aur zyada time milta hai:

$t_{c q} + t_{l o g i c} + t_{s u} \leq T + t_{s k e w}$

HOW ek EDA / STA tool ise dhundta hai (algorithm)

Static Timing Analysis (STA) vectors simulate nahi karta — yeh graph math karta hai:

Netlist ko Directed Acyclic Graph ki tarah model karo (nodes = gate pins, edges = delays).
Combinational feedback ko flip-flops par break karo (registers graph ke "cut points" hain).
Har node par Arrival Time (AT) compute karo = incoming paths par max (source AT + edge delay). Yeh ek forward topological pass hai.
Required Arrival Time (RAT) backward compute karo endpoints se $T$ , $t_{s u}$ use karke.
Slack = RAT − AT har node par. Sabse worst slack wala endpoint critical path ko terminate karta hai; max-delay predecessors ke along trace back karke ise reconstruct karo.

Worked examples

Forecast-then-Verify

Recall Answer padhne se pehle forecast karo

Q: Ek path mein 20 tiny gates hain har ek 0.1 ns ka; doosre mein 2 big gates hain har ek 3 ns ka. $t_{c q} = t_{s u} = 0.5$ ns. Kaun critical hai aur $f_{m a x}$ kya hai? Verify: Path 1 = $2$ ns, Path 2 = $6$ ns → Path 2 critical. $T_{m i n} = 0.5 + 6 + 0.5 = 7$ ns → $f_{m a x} \approx 142.9$ MHz. Gate count ne kisi ko bhi bewakoof nahi banaya jo delays sum karta hai.

Common mistakes (Steel-man + fix)

Recall Feynman: 12-saal ke bacche ko samjhao

Socho ek class bucket-brigade kar rahi hai ek tank fill karne ke liye, ek whistle par ek splash. Sabko apni bucket agle whistle se pehle pass karni hogi. Sabse slow baccha decide karta hai ki whistles ke beech kitna wait karna hoga — agar zyada fast whistle maaro, woh ek slow baccha bucket drop kar deta hai aur paani giir jaata hai (galat answer). Circuit mein "slowest kid" chain dhundhna hi critical path dhundhna hai. Faster jaane ke liye, ya toh slow bacche ko train karo (faster gates) ya unki lambi run ko do hisso mein baanto (ek register add karo).

Active-recall flashcards

Synchronous circuit mein critical path kya hota hai?

Woh register-to-register combinational path jisme sabse zyada total propagation delay ho (sabse kam timing slack); yeh max clock frequency set karta hai.

Setup timing inequality likho.

t_{c q} + t_{l o g i c} + t_{s u} \leq T + t_{s k e w}

Setup slack define karo.

slack = T + t_{s k e w} - (t_{c q} + t_{l o g i c} + t_{s u})

; critical path mein minimum slack hota hai.

Kya critical path woh hai jisme sabse zyada gates hain?

Nahi — woh hai jisme sabse zyada summed delay ho; gate count irrelevant hai.

Multi-input gate par, arrival time = ?

max(input arrival times) + gate delay, kyunki output aakhri input ka wait karta hai.

STA critical path kaise dhundta hai?

Netlist ko DAG model karo, arrival times ke liye forward pass (max use karke), required times ke liye backward pass, slack = RAT − AT, worst-slack endpoint trace karo.

Critical path chhoti karne ki ek technique.

Pipelining — ek register insert karo taaki ek lambi path chhote stages mein split ho jaaye (latency badhti hai,

f_{ma x}

badhta hai).

Capture-clock skew setup timing ko help karta hai ya hurt?

Positive capture skew setup relax karta hai (

+ t_{s k e w}

zyada time deta hai), lekin hold timing ko hurt karta hai.

Agar

t_{c q} = 1

t_{l o g i c} = 6

t_{s u} = 1

ns, no skew,

f_{ma x}

nikalo.

T_{min} = 8

ns →

f_{ma x} = 125

MHz.

Slack vs delay?

Delay = path par use hue time; slack = required time − arrival time (spare margin). Negative slack = violation.

Connections

Setup and Hold Time — woh constraints jinki violation critical path predict karta hai
Static Timing Analysis (STA) — woh tool/algorithm jo critical paths report karta hai
Clock Skew and Jitter — effective deadline ko modify karta hai
Pipelining — ek lambi critical path todne ki primary technique
Propagation Delay and Gate Sizing — $t_{l o g i c}$ ke ingredients
Maximum Clock Frequency — woh number jo critical path ultimately set karta hai
Synchronous Design Flow — flow mein critical-path checking kahan hoti hai