SRAM 6T cell structure and operation

WHAT is a 6T SRAM cell?

The four storage transistors form two inverters:

Inverter A: PMOS PL + NMOS NL, output node Q.
Inverter B: PMOS PR + NMOS NR, output node QB (Q-bar).

Cross-coupled means: Q drives inverter B's input, and QB drives inverter A's input.

Figure — SRAM 6T cell structure and operation

WHY cross-couple two inverters? (Derivation of bistability)

An inverter's transfer function is $V_{out}=f(V_{in})$ , monotonically decreasing: high in → low out.

Cross-coupling imposes two constraints simultaneously: $V_{QB}=f(V_Q)\qquad\text{and}\qquad V_Q=f(V_{QB})$

Substitute the second into the first: $V_Q=f\big(f(V_Q)\big)$

The composition $f\!\circ\!f$ is increasing (two decreasing functions compose to increasing). Plotting $V_Q$ (the identity line) against $f(f(V_Q))$ , they intersect three times:

Two stable intersections at the rails: $V_Q\approx 0$ and $V_Q\approx V_{DD}$ .
One unstable intersection at $V_Q=V_{QB}=V_M$ (the metastable point).

So the WHY of two inverters: one inverter alone just inverts; two in a loop create positive feedback, and positive feedback with high gain gives you two locked-in stable states = 1 bit of non-volatile-while-powered storage.

HOW the three operations work

Label: WL = word line (turns access transistors on), BL and BLB = the two bit lines. Access transistors AL (connects Q↔BL) and AR (connects QB↔BLB).

1. HOLD (retain)

WL = 0 → both access transistors OFF → storage nodes isolated.
The cross-coupled loop keeps Q and QB at opposite rails.
Why it holds: feedback continuously refills any charge lost to leakage. Static — no clock needed.

2. READ

Precharge both BL and BLB HIGH to $V_{DD}$ .
Raise WL = 1. Suppose Q=0, QB=1.
The side storing 0 (node Q) sinks current: BL discharges through AL+NL, while BLB stays high. A small differential voltage $\Delta V$ builds; a sense amplifier detects it.

3. WRITE

Drive the bit lines to the desired new value: to write 0 into Q, force BL=0, BLB=1.
Raise WL = 1. The access transistor AL must now be strong enough to overpower the internal PMOS PL that is holding Q high, and pull Q down through the low BL.

Worked examples

Common mistakes (steel-manned)

Active recall

Recall Quick self-test (hide and answer)

Why is SRAM called static? → feedback regenerates the bit; no refresh.
Which transistors store the data? → the 4 cross-coupled inverter transistors.
What is the cell ratio and which operation does it protect? → $CR=(W/L)_{NL}/(W/L)_{AL}$ ; protects read stability.
What is the pull-up ratio and which operation does it enable? → $PR=(W/L)_{PL}/(W/L)_{AL}$ ; enables write.
Why precharge both bit lines before read? → to sense a small differential $\Delta V$ quickly.
Where is the unstable point? → where $V_Q=V_{QB}=V_M$ , loop gain $>1$ .

Recall Feynman: explain to a 12-year-old

Imagine a see-saw with two kids. Whenever one goes up, they shove the other down — and that shove keeps them locked: up-down or down-up. That's how the memory remembers a 1 or a 0. There are two little gates (doors). Keep the doors closed and the see-saw just sits there remembering. Open the doors gently and you can look at which kid is up (reading). Open them and push hard on one side and you flip the see-saw to the other position (writing). Since the kids keep shoving each other, it never needs to be reminded — that's why it's called static.

Connections

DRAM 1T1C cell — contrast: dynamic, needs refresh, 1 transistor + 1 capacitor, denser.
CMOS Inverter — the building block whose transfer curve gives bistability.
Sense Amplifier — detects the small differential $\Delta V$ during read.
Static Noise Margin (SNM) — quantifies read/hold stability via the butterfly curve.
Bit line and Word line addressing — how cells are wired into an array.
Positive Feedback and Latches — the general regenerative-loop principle.

How many transistors are in a 6T SRAM cell and how are they split?

6 total = 4 cross-coupled inverter (storage) transistors + 2 access (switch) transistors.

Why is SRAM "static" (no refresh needed)?

Two cross-coupled inverters form a positive-feedback loop that continuously regenerates the stored bit while powered.

What creates the two stable states in an SRAM cell?

Cross-coupling makes

V_Q=f(f(V_Q))

; this increasing composition intersects the identity line at two stable rails plus one unstable middle point.

Where is the unstable (metastable) point of the cell?

Where

V_Q=V_{QB}=V_M

and the loop gain magnitude exceeds 1, so noise is amplified toward a rail.

Define the cell ratio (CR) and what it protects.

CR=(W/L)_{NL}/(W/L)_{AL}

; a large CR (strong pull-down vs access) prevents read disturb / keeps the cell read-stable (~~1.2–2). Define the pull-up ratio (PR) and what it enables. ::: $PR=(W/L)_{PL}/(W/L)_{AL}$ ; a small PR (weak pull-up) lets the access transistor override the PMOS during a write (~~≤1.8).

Why must both bit lines be precharged before a read?

So a small differential voltage

\Delta V

develops on the "0" side and a sense amplifier can detect the bit quickly.

During a write, which transistor must "win" and over what?

The access NMOS must overpower the internal PMOS pull-up to drag the storage node to the new value.

Why do read stability and write-ability pull transistor sizing in opposite directions?

Read wants a strong pull-down (large CR); write wants a weak pull-up (small PR); a robust cell balances both.

Which transistors actually store the data in a 6T cell?

Only the 4 inverter transistors; the 2 access transistors are just switches.

Concept Map

Hinglish (regional understanding)

Intuition Hinglish mein samjho

Dekho, SRAM ka 6T cell basically ek chhota sa "see-saw" hai jo do inverters se banta hai. Do inverters ko nose-to-tail cross-couple kar dete hain — matlab ek ka output doosre ka input. Is loop mein positive feedback ban jaata hai, isliye cell sirf do stable states mein reh sakta hai: Q=1 QB=0, ya Q=0 QB=1. Yahi ek bit store karta hai. Sabse important baat — ye static hai, matlab DRAM ki tarah refresh nahi karna padta, kyunki feedback loop khud hi bit ko continuously reinforce karta rehta hai jab tak power on hai.

6 transistor mein se sirf 4 store karte hain (do inverters), aur baaki 2 access transistors sirf doors hain jo word line (WL) se on hote hain. Read karne ke liye pehle dono bit lines (BL, BLB) ko VDD tak precharge karo, phir WL=1 karo — jis side pe 0 store hai wahan ki bit line thodi discharge hoti hai, aur sense amplifier chhota sa differential $\Delta V$ padhkar bit bata deta hai. Write karne ke liye bit lines pe naya value force karo aur WL=1 karke access transistor se node ko flip kar do.

Ab asli maza sizing mein hai. Read ke time bit line andar current push karti hai, isliye internal pull-down NMOS ko access NMOS se strong rakhna padta hai — isi ko cell ratio $CR$ bolte hain, taaki cell galti se flip na ho. Write ke time access transistor ko PMOS pull-up ko haraana padta hai, isliye PMOS ko weak rakhte hain — ye pull-up ratio $PR$ hai. Dhyaan do: read chahता hai strong pull-down, write chahता hai weak pull-up — dono opposite directions mein khinchte hain, aur achha SRAM cell dono ko balance karta hai. Yeh trade-off samajh liya to poora concept clear ho gaya.

WHAT is a 6T SRAM cell?

WHY cross-couple two inverters? (Derivation of bistability)

HOW the three operations work

1. HOLD (retain)

2. READ

3. WRITE

Worked examples

Common mistakes (steel-manned)

Active recall

Connections

Concept Map

Hinglish (regional understanding)

Go deeper — visual, from zero

Test yourself — Memory Technologies

Connections