SRAM 6T cell structure and operation — Hinglish notes

4.1.1 · Hardware › Memory Technologies

WHAT is a 6T SRAM cell?

Chaar storage transistors do inverters banate hain:

Inverter A: PMOS PL + NMOS NL, output node Q.
Inverter B: PMOS PR + NMOS NR, output node QB (Q-bar).

Cross-coupled ka matlab: Q inverter B ka input drive karta hai, aur QB inverter A ka input drive karta hai.

Figure — SRAM 6T cell structure and operation

WHY cross-couple two inverters? (Bistability ki derivation)

Ek inverter ka transfer function $V_{o u t} = f (V_{in})$ hota hai, monotonically decreasing: high in → low out.

Cross-coupling ek saath do constraints impose karta hai: $V_{QB} = f (V_{Q}) and V_{Q} = f (V_{QB})$

Doosre ko pehle mein substitute karo: $V_{Q} = f (f (V_{Q}))$

Composition $f \circ f$ increasing hai (do decreasing functions compose hokar increasing ban jaate hain). $V_{Q}$ (identity line) ko $f (f (V_{Q}))$ ke against plot karo, to ye teen baar intersect karte hain:

Do stable intersections rails par: $V_{Q} \approx 0$ aur $V_{Q} \approx V_{D D}$ .
Ek unstable intersection $V_{Q} = V_{QB} = V_{M}$ par (metastable point).

Toh do inverters ka WHY yeh hai: akela inverter sirf invert karta hai; loop mein do inverters positive feedback create karte hain, aur high gain ke saath positive feedback do locked-in stable states deta hai = 1 bit of non-volatile-while-powered storage.

HOW teen operations kaam karti hain

Label: WL = word line (access transistors ko on karta hai), BL aur BLB = do bit lines. Access transistors AL (Q↔BL connect karta hai) aur AR (QB↔BLB connect karta hai).

1. HOLD (retain)

WL = 0 → dono access transistors OFF → storage nodes isolated.
Cross-coupled loop Q aur QB ko opposite rails par rakhta hai.
Kyun hold karta hai: feedback continuously koi bhi charge jo leakage se khoye use refill karta rehta hai. Static — koi clock zaroori nahi.

2. READ

Precharge dono BL aur BLB ko $V_{D D}$ tak HIGH karo.
WL = 1 karo. Maano Q=0, QB=1.
Jo side 0 store kar rahi hai (node Q), woh current sink karta hai: BL, AL+NL se discharge hota hai, jabki BLB high rehta hai. Ek chota differential voltage $Δ V$ build hota hai; ek sense amplifier ise detect karta hai.

3. WRITE

Bit lines ko desired nayi value par drive karo: Q mein 0 likhne ke liye, BL=0, BLB=1 force karo.
WL = 1 karo. Access transistor AL ko ab itna strong hona chahiye ki internal PMOS PL ko — jo Q ko high hold kar raha hai — overpower kar sake, aur Q ko low BL ke through neeche kheench sake.

Worked examples

Common mistakes (steel-manned)

Active recall

Recall Quick self-test (chhupaao aur jawaab do)

SRAM ko static kyun kaha jaata hai? → feedback bit ko regenerate karta hai; refresh nahi chahiye.
Kaun se transistors data store karte hain? → 4 cross-coupled inverter transistors.
Cell ratio kya hai aur yeh kaunsi operation protect karta hai? → $C R = (W / L)_{N L} / (W / L)_{A L}$ ; read stability protect karta hai.
Pull-up ratio kya hai aur yeh kaunsi operation enable karta hai? → $P R = (W / L)_{P L} / (W / L)_{A L}$ ; write enable karta hai.
Read se pehle dono bit lines precharge kyun karte hain? → taaki ek chota differential $Δ V$ jaldi sense ho sake.
Unstable point kahan hota hai? → jahan $V_{Q} = V_{QB} = V_{M}$ ho, loop gain $> 1$ ho.

Recall Feynman: 12-saal ke bacche ko samjhao

Socho ek see-saw par do bacche hain. Jab bhi ek upar jaata hai, woh doosre ko neeche dhakelta hai — aur yeh dhakka unhe lock rakhta hai: upar-neeche ya neeche-upar. Isi tarah memory 1 ya 0 yaad rakhti hai. Do chote gates (darwaze) hote hain. Darwaze band rakho aur see-saw bas wahan baith kar yaad karta rehta hai. Darwaze dheere se kholo aur tum dekh sakte ho kaun sa baccha upar hai (reading). Unhe kholo aur ek taraf zor se push karo aur see-saw dusri position mein palat jaata hai (writing). Kyunki bacche ek-doosre ko dhakelte rehte hain, ise kabhi yaad dilane ki zaroorat nahi — isliye ise static kaha jaata hai.

Connections

DRAM 1T1C cell — contrast: dynamic, refresh chahiye, 1 transistor + 1 capacitor, denser.
CMOS Inverter — woh building block jiska transfer curve bistability deta hai.
Sense Amplifier — read ke dauran chota differential $Δ V$ detect karta hai.
Static Noise Margin (SNM) — butterfly curve se read/hold stability quantify karta hai.
Bit line and Word line addressing — cells ko array mein kaise wire kiya jaata hai.
Positive Feedback and Latches — general regenerative-loop principle.

6T SRAM cell mein kitne transistors hote hain aur kaise split hote hain?

Kul 6 = 4 cross-coupled inverter (storage) transistors + 2 access (switch) transistors.

SRAM "static" kyun hai (refresh nahi chahiye)?

Do cross-coupled inverters ek positive-feedback loop banate hain jo power rahne tak stored bit ko continuously regenerate karta hai.

SRAM cell mein do stable states kya create karta hai?

Cross-coupling ki wajah se

V_{Q} = f (f (V_{Q}))

hota hai; yeh increasing composition identity line ko do stable rails par aur ek unstable middle point par intersect karta hai.

Cell ka unstable (metastable) point kahan hota hai?

Jahan

V_{Q} = V_{QB} = V_{M}

ho aur loop gain ka magnitude 1 se zyada ho, isliye noise ek rail ki taraf amplify hoti hai.

Cell ratio (CR) define karo aur yeh kya protect karta hai.

C R = (W / L)_{N L} / (W / L)_{A L}

; bada CR (access ke muqable strong pull-down) read disturb prevent karta hai / cell ko read-stable rakhta hai (1.2–2). Pull-up ratio (PR) define karo aur yeh kya enable karta hai. ::: $P R = (W / L)_{P L} / (W / L)_{A L}$ ; chhota PR (weak pull-up) access transistor ko write ke dauran PMOS override karne deta hai (≤1.8).

Read se pehle dono bit lines precharge kyun kiye jaate hain?

Taaki "0" side par ek chota differential voltage

Δ V

develop ho aur sense amplifier bit ko jaldi detect kar sake.

Write ke dauran, kaun sa transistor "jeetta" hai aur kisse?

Access NMOS ko internal PMOS pull-up ko overpower karna hota hai taaki storage node ko nayi value par kheench sake.

Read stability aur write-ability transistor sizing ko opposite directions mein kyun pull karte hain?

Read ek strong pull-down chahta hai (bada CR); write ek weak pull-up chahta hai (chhota PR); ek robust cell dono ko balance karta hai.

6T cell mein actually data kaun se transistors store karte hain?

Sirf 4 inverter transistors; 2 access transistors bas switches hain.