DRAM 1T1C cell structure

HOW does a cell operate? (Derive it from charge)

The capacitor stores charge: $Q = C_s \cdot V_{cell}$

Why this? A capacitor's defining relation is $Q = CV$ . The bit is the voltage $V_{cell}$ on $C_s$ . High $V$ = "1", low $V$ = "0".

Writing

Drive BL to the desired voltage ( $V_{DD}$ for 1, $0$ for 0).
Raise WL → transistor conducts → $C_s$ charges/discharges to match BL.
Lower WL → transistor off → charge is trapped on the isolated storage node.

Why lower WL last? Once the tap closes, the storage node floats, so the charge has nowhere easy to go — it's now "stored".

Reading — the destructive part

Reading is where the physics gets interesting. The bitline has its own big capacitance $C_{BL}$ (it's a long wire touching many cells), and $C_{BL} \gg C_s$ .

Before reading, we precharge the bitline to $V_{DD}/2$ . Then we raise WL and let $C_s$ share charge with $C_{BL}$ .

Why derive it this way? The transistor just connects two capacitors; no charge is created or destroyed, so charge conservation gives everything. The factor $\dfrac{C_s}{C_s+C_{BL}}$ tells us the tiny cell only nudges the huge bitline by a few tens of millivolts — which is why we need a sense amplifier to amplify $\Delta V$ back to a full logic level.

Why "destructive"? After charge sharing, $V_{cell}$ is no longer at its original value (it got diluted toward $V_{DD}/2$ ). The read ruins the stored bit, so the sense amp must write the bit back every read.

Refresh — WHY DRAM forgets

The leakage discharge follows an RC decay: $V_{cell}(t) = V_{DD}\, e^{-t/(R_{leak}C_s)}$

Why exponential? A charged capacitor discharging through a resistance $R_{leak}$ satisfies $C\frac{dV}{dt} = -V/R_{leak}$ , whose solution is the exponential above. Refresh must happen before $V_{cell}$ drops below the sense-amp's detectable margin.

Worked Examples

Common Mistakes (Steel-manned)

Recall Feynman: explain to a 12-year-old

Imagine every bit is a little water cup with a tap on it. Full cup = 1, empty cup = 0. To read the cup, you connect it to a giant tank; the water level barely changes, so you need a super-sensitive gauge (the sense amp) to tell "was it full or empty?". But connecting to the tank spills your cup, so you have to refill it right after. Also, the cups leak slowly, so every 64 milliseconds a helper walks around topping up all the full cups. That topping-up is called refresh, and it's why we call it Dynamic RAM.

Active Recall

What are the two components of a 1T1C DRAM cell?

One access (NMOS) transistor and one storage capacitor

C_s

Which line connects to the transistor gate?

The wordline (WL).

Which line carries charge in/out during read/write?

The bitline (BL).

Why is a DRAM read called "destructive"?

Charge sharing between

C_s

and

C_{BL}

dilutes the cell voltage, so the bit must be rewritten by the sense amp.

Write the signal-swing formula on the bitline.

\Delta V = \frac{C_s}{C_s+C_{BL}}\left(V_{cell}-\frac{V_{DD}}{2}\right)

Why is the bitline precharged to

V_{DD}/2

So a "1" swings up and a "0" swings down symmetrically for the differential sense amp.

Why must the swing formula produce a small

\Delta V

Because

C_{BL}\gg C_s

, so the tiny cell only nudges the big bitline by tens of mV.

What does the "D" in DRAM stand for and why?

Dynamic — the capacitor leaks, so data must be periodically refreshed.

Typical refresh interval?

~64 ms (≈32 ms at high temperature).

Why 1T1C instead of SRAM's 6T?

Far higher density (fewer transistors per bit) → cheaper per bit.

Charge stored on a cell holding "1"?

Q = C_s V_{DD}

What amplifies the small bitline signal back to a full logic level?

The sense amplifier.

Connections

SRAM 6T cell — the fast, non-destructive, low-density counterpart.
Sense Amplifiers — needed because $\Delta V$ is tiny.
DRAM Refresh — direct consequence of capacitor leakage.
Charge Sharing — the physics behind destructive reads.
Bitline and Wordline Architecture — how cells are wired into arrays.
Capacitor Q=CV — the fundamental relation storing the bit.

Concept Map

Hinglish (regional understanding)

Intuition Hinglish mein samjho

Dekho, DRAM ka ek bit matlab ek chhoti si "paani ki balti" — yaani ek capacitor ( $C_s$ ). Balti bhari = 1, khaali = 0. Us balti ka nal (tap) hota hai ek transistor. Isliye naam pada 1T1C = 1 Transistor + 1 Capacitor. Sirf do cheezein, taaki ek chip par maximum bits fit ho jayein — density zyada, cost per GB kam. Yahi wajah hai ki tumhare laptop ki main RAM DRAM hoti hai, cache SRAM.

Ab read ka twist: bitline ek lambi wire hai jiska apna bada capacitance $C_{BL}$ hota hai, aur $C_{BL} \gg C_s$ . Read se pehle bitline ko $V_{DD}/2$ pe precharge karte hain. Fir wordline on karte ho, tap khulta hai, aur chhoti balti apna charge badi bitline ke saath share karti hai. Charge conservation se signal swing nikalta hai: $\Delta V = \frac{C_s}{C_s+C_{BL}}(V_{cell}-V_{DD}/2)$ . Kyunki $C_s$ bahut chhota hai, ye swing sirf 30–60 mV hota hai — isliye sense amplifier chahiye jo isko full logic level tak amplify kare.

Ek important baat: read destructive hota hai. Charge share hone ke baad cell ka original voltage kharab ho jata hai, isliye sense amp ko bit wapas likhna padta hai har read ke baad. Aur capacitor dheere-dheere leak karta hai (junction + subthreshold leakage), toh har ~64 ms mein poori chip ko read-and-rewrite karna padta hai — isko refresh kehte hain, aur isi "dynamic" behaviour ki wajah se naam hai DRAM. Yaad rakho: One Tap, One Cup — Dilute, Sense, Refill, Refresh.

WHY does DRAM use only 1T1C?

WHAT is the cell made of?

HOW does a cell operate? (Derive it from charge)

Writing

Reading — the destructive part

Refresh — WHY DRAM forgets

Worked Examples

Common Mistakes (Steel-manned)

Active Recall

Connections

Concept Map

Hinglish (regional understanding)

Go deeper — visual, from zero

Test yourself — Memory Technologies

Connections