Memory Technologies

Question 1

(a) Set $V(t_{ret}) = V_{ref}$: $V_{ref} = V_{DD}e^{-t_{ret}/RC}$. $t_{ret} = RC\ln\!\left(\frac{V_{DD}}{V_{ref}}\right).$ (2 marks derivation) $RC = 8\times10^{12}\times25\times10^{-15} = 0.2\ \text{s}$. (1) $\ln(1.2/0.6)=\ln 2 = 0.6931$. (1) $t_{ret} = 0.2\times0.6931 = 0.13863\ \text{s} = 138.6\ \text{ms}$. (1)

(b) All $2^{16}=65536$ rows in $t_{ret}$: one row every $t_{REFI} = t_{ret}/65536 = 0.13863/65536 = 2.1153\times10^{-6}\ \text{s} \approx 2115\ \text{ns}$. (4) (This is comparable to the JEDEC $7.8\ \mu s$ figure scaled for row count / margin.)

(c) With all-bank refresh covering 8 rows/command, number of commands per window $= 65536/8 = 8192$. Time busy $= 8192\times350\ \text{ns} = 2.8672\ \text{ms}$. (2) Overhead $= 2.8672/138.63 = 0.02068 \approx 2.07\%$. (2) Scaling comment: as $C$ shrinks, stored charge $Q=CV$ drops, retention worsens (shorter $t_{ret}$), so $t_{REFI}$ falls and $t_{RFC}$ grows with row count → refresh overhead rises, eating bandwidth and power. This drives temperature-compensated refresh and larger cells / trench capacitors. (2)

(d) From (a), $t_{ret}/(RC) = \ln(V_{DD}/V_{ref})$, a ratio of voltages only — no $C$ or $R$. Thus the number of time constants is fixed by the voltage margin, independent of $C$. (3) Physical significance: absolute $t_{ret}=RC\ln(\cdot)$ still depends on the product $RC$. As nodes scale, $C$ decreases but leakage $R$ also changes (often decreasing due to thinner oxides / higher fields), so $RC$ typically shrinks → retention degrades even though the fractional margin form is invariant. Designers must preserve the $RC$ product, not just the voltage ratio. (2)

Question 2

(a) Reference sits at midpoint, so distance from a level mean to nearest ref is $\Delta/2$ where $\Delta = 0.8$ V spacing, i.e. distance $=0.4$ V. Error when a Gaussian sample crosses: $P_e = Q\!\left(\frac{\Delta/2}{\sigma}\right) = \tfrac12\,\text{erfc}\!\left(\frac{\Delta/2}{\sigma\sqrt2}\right).$ (3) $\frac{\Delta/2}{\sigma} = \frac{0.4}{0.15} = 2.6667$. (1) $Q(2.6667) = \tfrac12\text{erfc}(2.6667/\sqrt2)=\tfrac12\text{erfc}(1.8856)$. $\approx 3.83\times10^{-3}$. (2) (Levels adjacent on both sides double for interior levels, but use this as per-bit bound.)

(b) RBER $\approx 3.83\times10^{-3}$. Expected errors per 32768-bit page $= 32768\times3.83\times10^{-3} \approx 125.5$ bit errors. (4)

(c) Poisson mean $\lambda = \text{RBER}\times4096 = 3.83\times10^{-3}\times4096 = 15.69$. (1) $P_{uc}=P(X>t)=1-\sum_{k=0}^{t}\frac{\lambda^k e^{-\lambda}}{k!}.$ (3) For $t=8$, $\lambda=15.69$: $P_{uc}=1-\sum_{k=0}^{8}\frac{15.69^k e^{-15.69}}{k!}\approx 0.978$. (2) Interpretation: $t=8$ is far too weak here ($\lambda\gg t$) → almost every codeword fails; MLC needs much stronger ECC (or lower RBER). (bonus insight)

(d) Fixed window $W$ split into $L$ levels: mean spacing $\Delta = W/(L-1)$. So MLC ($L=4$): $\Delta=W/3$; TLC ($L=8$): $\Delta=W/7$; QLC ($L=16$): $\Delta=W/15$. (3) RBER $=Q(\Delta/2\sigma)$. Since $Q$ decays like $e^{-x^2/2}$, halving $\Delta$ roughly squares-then-worse the error. Going MLC→TLC more than doubles $L-1$ (3→7), so $\Delta$ shrinks by ~2.3×, and the exponent $\propto \Delta^2$ collapses → RBER rises by orders of magnitude, demanding LDPC / stronger BCH. (3)

Question 3

(a) 6T cell: two cross-coupled inverters (M1/M2 pull-down NMOS, M3/M4 pull-up PMOS) storing complementary nodes Q, Q̄; two access NMOS (M5/M6) gated by the word line connecting Q/Q̄ to bit lines BL/BL̄. (2) Hold: positive feedback — if Q high, it turns off the opposite pull-down keeping Q̄ low, which keeps Q high; a stable bistable latch. (1) Read stability: during read both BL precharged high; the "0" storage node (say Q=0) is pulled up through the access transistor M5 while the pull-down M1 tries to keep it low. The node voltage rises to a divider value set by M5 (access) vs M1 (pull-down). To avoid flipping, this bump must stay below the inverter trip point $V_{trip}$. Requires cell ratio $\beta = \frac{(W/L)_{pulldown}}{(W/L)_{access}} > 1$ (typically $\approx1.2$–$2$): pull-down stronger than access. (3)

(b) Peak $= 6400\times10^6\ \text{transfers/s}\times64\ \text{bits} \div 8 = 6400\times10^6\times8\ \text{B}$ $= 51.2\times10^9\ \text{B/s} = 51.2\ \text{GB/s}$. (2) Sustained $= 0.68\times51.2 = 34.816\ \text{GB/s}$. (2)

(c) Each CAM entry compares its 40-bit tag against the search word in parallel via a match line: any mismatching bit pulls the precharged match line low; a fully matching row keeps it high. All 1024 rows compare simultaneously → constant time. A priority encoder converts the (one-hot) match lines to an address in $O(1)$. (3) Cost: CAM cells are ~2–3× the transistors of SRAM (extra compare logic per bit), match-line precharge/discharge every cycle → high dynamic energy; area and power scale with entries×width. SRAM only reads one addressed row. (2) Gate count: $1024$ entries $\times 40$ bits $= 40960$ bit-comparisons (each an XNOR/XOR) activated per lookup $\Rightarrow \mathcal{O}(4\times10^4)$ comparison gates. (3)

[
 {"claim":"DRAM retention time = RC ln(VDD/Vref) = 138.6 ms","code":"R=8e12; C=25e-15; VDD=1.2; Vref=0.6; tret=R*C*log(VDD/Vref); result = abs(float(tret)-0.13863)<1e-4"},
 {"claim":"Refresh interval tREFI ~ 2115 ns","code":"R=8e12; C=25e-15; tret=R*C*log(2); trefi=tret/65536; result = abs(float(trefi)*1e9-2115)<5"},
 {"claim":"Refresh overhead ~ 2.07%","code":"R=8e12;C=25e-15;tret=R*C*log(2);busy=(65536/8)*350e-9;ov=busy/tret; result = abs(float(ov)-0.0207)<5e-4"},
 {"claim":"MLC raw error prob Q(0.4/0.15) ~ 3.83e-3","code":"from sympy import erfc,sqrt,Rational; x=Rational(4,10)/Rational(15,100); Pe=(erfc(x/sqrt(2))/2).evalf(); result = abs(float(Pe)-3.83e-3)<1e-4"},
 {"claim":"DDR5 6400MT/s x64bit peak = 51.2 GB/s","code":"bw=6400e6*64/8; result = abs(bw-51.2e9)<1e6"},
 {"claim":"Sustained 68% = 34.816 GB/s","code":"result = abs(0.68*51.2-34.816)<1e-6"},
 {"claim":"CAM lookup activates ~40960 comparisons","code":"result = 1024*40==40960"}
]