SRAM read - write operations — Hardware notes

80/20 core: An SRAM cell is two cross-coupled inverters (a latch) plus two access transistors. Reading senses the tiny voltage the stored bit puts on the bit-lines; writing forces the bit-lines hard enough to flip the latch. Everything below is just "how strong must each transistor be so read doesn't destroy data and write actually succeeds."

Read Operation — HOW it works

Steps (say cell holds Q=0, Q̄=1):

Pre-charge: drive $BL=\overline{BL}=V_{DD}$ , then float them.
Assert WL: M5, M6 turn on, connecting $Q\to BL$ and $\overline{Q}\to \overline{BL}$ .
Node $Q=0$ pulls $BL$ down through access transistor M5 + pull-down M1. Node $\overline{Q}=1$ keeps $\overline{BL}$ high.
A small $\Delta V = V_{\overline{BL}} - V_{BL}$ develops. Sense amp latches it.

Why pre-charge high? — Because pulling down is easy (NMOS is strong); we only need the cell to sink current, not source it.

Read stability — the deadly constraint

During read, $Q=0$ is connected via M5 to $BL$ which sits near $V_{DD}$ . Current flows into node Q, raising its voltage to $V_Q > 0$ . If $V_Q$ rises above the switching threshold of the other inverter, the cell flips → data destroyed (read upset).

Formula Read-stability condition (why the ratio matters)

Node $Q$ forms a voltage divider between the "on" access transistor M5 (pulling up toward $BL$ ) and the "on" pull-down M1 (pulling to ground). Approximating both in the linear/saturation regime, the raised node voltage is roughly $V_Q \approx V_{DD}\cdot \frac{R_{M1}}{R_{M1}+R_{M5}} \;\Rightarrow\; \text{keep } V_Q < V_{TH,inv}$ We need M1 stronger (lower resistance) than M5. Define the cell ratio $CR = \frac{(W/L)_{\text{pull-down}}}{(W/L)_{\text{access}}} > 1 \quad(\text{typically }\approx 1.2\text{–}2)$ WHY: a bigger, stronger pull-down keeps $V_Q$ low so the latch doesn't tip.

Write Operation — HOW it works

Steps (cell holds Q=1, we want to write 0):

Drive $BL=0$ , $\overline{BL}=V_{DD}$ .
Assert WL → M5, M6 on.
$BL=0$ pulls node $Q$ down through M5, fighting the cell's PMOS pull-up M2. To flip, M5 must win: $V_Q$ must fall below the trip point so the other inverter flips $\overline{Q}$ high, which then reinforces $Q=0$ (regenerative).

Formula Write condition (why the

opposite ratio matters) Now node $Q$ is a divider between access transistor M5 (pulling to $BL=0$ ) and pull-up PMOS M2 (pulling to $V_{DD}$ ). To force $V_Q$ below the trip point we need M5 stronger than the PMOS pull-up. Two equivalent ways to state the sizing rule: $PR = \frac{(W/L)_{\text{pull-up}}}{(W/L)_{\text{access}}} < 1 \quad(\text{pull-up must be weaker than access})$ or, in the form most write-margin design rules use, $\frac{(W/L)_{\text{access}}}{(W/L)_{\text{pull-up}}} \gtrsim 1.2\text{–}1.5$ i.e. make the access transistor at least ~1.2–1.5× stronger than the PMOS pull-up so it overpowers it.

Worked Examples

Common Mistakes

Feynman

Recall Explain to a 12-year-old

Imagine two kids on a see-saw who agree: "you go up, I go down." That locked position remembers a 1 or 0. To read, you gently touch each side and feel which one is up — but touch too hard and you knock them over (that's why the down-side kid must be sturdy). To write, you deliberately shove one side down hard until they swap seats. So reading = gentle feel, writing = firm shove; the transistor sizes decide how gentle or firm.

Flashcards

How many transistors in a standard SRAM cell and what are they?

6 — 4 form two cross-coupled inverters (latch), 2 are access/pass transistors gated by the word-line.

Why is an SRAM read non-destructive (unlike DRAM)?

The cross-coupled latch is actively powered and restores its state; it isn't stored as decaying charge, so no refresh/rewrite is needed (if cell ratio > 1).

What is done to the bit-lines before a read?

Both BL and BL̄ are pre-charged to VDD, then left floating, so the cell can pull one down.

Define cell ratio (CR) and its required range.

CR = (W/L)pull-down / (W/L)access, must be > 1 (≈1.2–2) to keep node voltage low during read → read stability.

Define pull-up ratio (PR) and its constraint.

PR = (W/L)pull-up / (W/L)access; must be < 1 for write to succeed (pull-up weaker than access). Equivalently (W/L)access/(W/L)pull-up ≳ 1.2–1.5.

What is read upset?

During read, the access transistor raises the '0' storage node's voltage; if it exceeds the inverter trip point the latch flips and the stored bit is destroyed.

During a write, why drive both bit-lines?

To force one node low and the other high, letting the regenerative cross-coupling reliably flip and hold the new state.

Cell stores Q=1: on a read, which bit-line droops?

BL̄ (connected to Q̄=0) droops; BL stays high.

What fundamental trade-off constrains the access transistor?

It must be weak enough not to disturb the cell on read (CR>1) yet strong enough to flip it on write — a competing sizing requirement.

Connections

DRAM read-write operations — destructive read + refresh vs SRAM's static latch.
Sense amplifiers — amplifies the small $\Delta V$ on the bit-lines.
CMOS inverter — the building block; its trip point sets stability.
Static Noise Margin (SNM) — quantifies read/hold stability (butterfly curve).
Cache memory — where 6T SRAM is used (L1/L2).
MOSFET sizing (W/L) — origin of CR and PR.

Concept Map

Hinglish (regional understanding)

Intuition Hinglish mein samjho

Dekho, SRAM ka ek cell basically do cross-coupled inverters ka latch hai — do inverter ek doosre ko hold karte hain, isliye woh ek stable "1" ya "0" yaad rakhte hain bina refresh ke. Yahi reason hai ki SRAM fast hota hai aur cache mein use hota hai. Do extra access transistors (M5, M6) word-line se control hote hain jo cell ko bit-lines se connect karte hain.

Read karte time hum dono bit-lines ko pehle VDD tak pre-charge karte hain, phir WL on karte hain. Jis node pe 0 store hai woh apni bit-line ko thoda neeche kheechta hai, aur sense amplifier is chhote se difference (ΔV) ko amplify karke bata deta hai ki bit 1 tha ya 0. Yaad rakho — read destructive nahi hai (DRAM ke ulat), kyunki latch khud ko restore kar leta hai. Par ek catch hai: agar access transistor bahut strong hua to read ke time storage node ka voltage upar chala jaayega aur cell flip ho sakta hai — ise read upset kehte hain. Isse bachne ke liye pull-down transistor ko strong rakhte hain, yaani cell ratio CR > 1.

Write karte time hum bit-lines ko force karte hain (jo value chahiye), WL on, aur access transistor ko cell ke PMOS pull-up ko haraana padta hai taaki node flip ho jaaye. Iske liye access transistor pull-up se strong hona chahiye — yani pull-up ratio PR < 1, ya seedhe shabdon mein (W/L)access / (W/L)pull-up kam se kam 1.2–1.5 hona chahiye. Poora khel yahi tension hai: read ke liye access weak chahiye, write ke liye access strong chahiye. Isi balance mein transistor sizing hoti hai. Mnemonic yaad rakho: "READ the Pull-Down, WRITE past the Pull-Up."

SRAM read - write operations

The 6T Cell — WHAT it is

Read Operation — HOW it works

Read stability — the deadly constraint

Write Operation — HOW it works

Worked Examples

Common Mistakes

Feynman

Flashcards

Connections

Concept Map

Hinglish (regional understanding)

Go deeper — visual, from zero

Test yourself — Memory Technologies

Connections