SRAM read - write operations: Exercises — Hardware deep dive

Before we begin, one shared picture we will reuse in almost every problem: the voltage divider on node Q. During a read or a write, the internal node $Q$ is being tugged toward two different voltages by two "on" transistors at once. We model each transistor as a plain resistor and ask: where does the node settle?

The figure above is our master template. Read it like this: the black dot in the middle is node $Q$ . The green line is the pull-down resistor $R_{P D}$ tying $Q$ down to ground (0 V). The orange line is the access resistor $R_{A C C}$ tying $Q$ to the bit-line $B L$ . The dashed red line is the pull-up resistor $R_{P U}$ tying $Q$ to $V_{D D}$ — this branch only matters during a write. In every problem below we just decide which two of these three resistors are active and plug them into the one divider equation.

Formula The one equation behind everything

Suppose node $Q$ is tugged toward a high voltage $V_{hi}$ through resistor $R_{hi}$ (the resistor connected to the $V_{hi}$ side) and toward a low voltage $V_{l o}$ through resistor $R_{l o}$ (the resistor connected to the $V_{l o}$ side). Then $V_{Q} = V_{l o} + (V_{hi} - V_{l o}) \cdot \frac{R _{l o}}{R _{hi} + R _{l o}}$ Read the fraction as "the OTHER side's resistance over the total": the closer $Q$ sits to $V_{hi}$ , the smaller $R_{hi}$ must be. So $V_{Q}$ leans toward whichever side has the smaller resistance. That single sentence decides read stability and write success.

Read (stored 0): $V_{hi} = V_{D D}$ via $R_{hi} = R_{A C C}$ ; $V_{l o} = 0$ via $R_{l o} = R_{P D}$ . → $V_{Q} = V_{D D} \cdot \frac{R _{P D}}{R _{P D} + R _{A C C}}$ .
Write 0 (was holding 1): $V_{hi} = V_{D D}$ via $R_{hi} = R_{P U}$ ; $V_{l o} = 0$ via $R_{l o} = R_{A C C}$ . → $V_{Q} = V_{D D} \cdot \frac{R _{A C C}}{R _{A C C} + R _{P U}}$ .

Level 1 — Recognition

Recall Solution

M1, M3 — NMOS pull-downs (one per inverter). They tie the internal node to ground when that node should be a logic 0.
M2, M4 — PMOS pull-ups (one per inverter). They tie the node to $V_{D D}$ for a logic 1.
M1+M2 form one inverter, M3+M4 the other; cross-coupling them makes the bistable latch.
M5, M6 — NMOS access (pass) transistors, gated by the word-line WL, connecting $Q \to B L$ and $\overline{Q} \to \overline{B L}$ .

Why bistable — the butterfly picture. Each inverter's output-vs-input curve is an S-shape. Plotting one inverter's curve and the other's mirrored on the same axes gives a butterfly: they cross at exactly two outer points (the two stable states, $Q = 1$ or $Q = 0$ ) and one middle point (unstable). The largest square you can fit into either wing is the Static Noise Margin (SNM) — how much accidental voltage the node can absorb before the latch flips. See the figure below.

Recall Solution

Both bit-lines are driven high to $V_{D D}$ , then floated (left disconnected so they hold their charge). The cell then pulls one of them slightly down. We charge high because the cell's NMOS pull-down is good at sinking current (pulling down) but the cell cannot easily source current to push a line above $V_{D D}$ .

Level 2 — Application

Recall Solution

Node $Q = 0$ is at ground, connected through M5 to $B L$ (sitting at $V_{D D}$ ). Current flows from $B L$ into ground → $B L$ droops. Node $\overline{Q} = 1$ is at $V_{D D}$ and cannot pull $\overline{B L}$ below $V_{D D}$ , so $\overline{B L}$ stays high. How the sense amp turns that droop into a logic value: it is a small cross-coupled amplifier that watches the difference $\overline{B L} - B L$ . Whichever bit-line is lower gets driven all the way to 0, the higher one all the way to $V_{D D}$ — it amplifies a tiny $Δ V$ (tens of mV) into a full logic level. Here $B L$ drooped, so the amp latches $B L \to 0, \overline{B L} \to V_{D D}$ . By the convention "value of node $Q$ = value on $B L$ ", $Q = 0$ reads a 0. ✔

Recall Solution

Use the divider with $V_{hi} = V_{D D}$ through $R_{hi} = R_{A C C}$ , $V_{l o} = 0$ through $R_{l o} = R_{P D}$ : $V_{Q} = V_{D D} \cdot \frac{R _{P D}}{R _{P D} + R _{A C C}} = 1.0 \cdot \frac{2}{2 + 8} = 0.20 V$ Since $0.20 < 0.5 = V_{T H}$ , node $Q$ never climbs to the other inverter's trip point → stable, no read upset. ✔ Cell ratio $C R = R_{A C C} / R_{P D} = 8/2 = 4$ ; the pull-down is 4× stronger — very safe.

Recall Solution

$C R = \frac{( W / L ) _{P D}}{( W / L ) _{A C C}} = \frac{1/ R _{P D}}{1/ R _{A C C}} = \frac{R _{A C C}}{R _{P D}} = \frac{8}{2} = 4$ $C R = 4 > 1$ , so the pull-down dominates during read. ✔

Level 3 — Analysis

Recall Solution

Now the low side is the bit-line and the high side is the pull-up ( $V_{hi} = V_{D D}$ via $R_{hi} = R_{P U}$ ; $V_{l o} = 0$ via $R_{l o} = R_{A C C}$ ): $V_{Q} = V_{D D} \cdot \frac{R _{A C C}}{R _{A C C} + R _{P U}} = 1.0 \cdot \frac{5}{5 + 10} = 0.333 V$ We need $V_{Q} < V_{T H} = 0.5$ to trip the far inverter. $0.333 < 0.5$ → write succeeds. ✔ Intuition: the access transistor ( $R = 5$ k) is stronger than the pull-up ( $R = 10$ k), so it wins the tug-of-war and drags $Q$ down. Here $P R = R_{A C C} / R_{P U} = 5/10 = 0.5 < 1$ — writable.

Recall Solution

$V_{Q} = 1.0 \cdot \frac{5}{5 + 1} = 0.833 V$ $0.833 > 0.5$ → $V_{Q}$ never crosses the trip point → write FAILS. ✘ The over-strong PMOS holds $Q$ up. Here $P R = 5/1 = 5 > 1$ (access weaker than pull-up), consistent with failure. Fix: weaken the pull-up (smaller $W / L$ → larger $R_{P U}$ ) or widen the access transistor (smaller $R_{A C C}$ ) so access beats pull-up.

Recall Solution

Set $V_{Q} = V_{T H}$ (the tipping edge) and solve: $0.5 = 1.0 \cdot \frac{R _{A C C}}{R _{A C C} + 1} \Rightarrow 0.5 (R_{A C C} + 1) = R_{A C C} \Rightarrow R_{A C C} = 1 k Ω$ So $R_{A C C} \leq 1 k Ω$ writes. At exactly $1 k Ω$ the access equals the pull-up ( $V_{Q} = 0.5$ , right on the trip point — marginal). To have margin, make $R_{A C C}$ noticeably smaller than $R_{P U}$ . ✔

Level 4 — Synthesis

Recall Solution

Strategy from the mnemonic "READ the Pull-Down, WRITE past the Pull-Up": make the pull-down strong and keep the pull-up at minimum width (weakest allowed), and widen the access moderately. Choose $m_{P D} = 4$ (strong), $m_{P U} = 1$ (reference = weakest allowed), $m_{A C C} = 2$ . Resistances: $R_{P D} = 4/4 = 1 k Ω$ , $R_{P U} = 4/1 = 4 k Ω$ , $R_{A C C} = 4/2 = 2 k Ω$ .

Read check ( $Q$ between $B L \approx V_{D D}$ via $R_{A C C}$ and gnd via $R_{P D}$ ): $V_{Q}^{r e a d} = 1.0 \cdot \frac{R _{P D}}{R _{P D} + R _{A C C}} = \frac{1}{1 + 2} = 0.333 V < 0.5 ✓$ Write check ( $Q$ between $B L = 0$ via $R_{A C C}$ and $V_{D D}$ via $R_{P U}$ ): $V_{Q}^{w r i t e} = 1.0 \cdot \frac{R _{A C C}}{R _{A C C} + R _{P U}} = \frac{2}{2 + 4} = 0.333 V < 0.5 ✓$ Both pass. $C R = R_{A C C} / R_{P D} = 2/1 = 2 > 1$ (read-safe); $P R = R_{A C C} / R_{P U} = 2/4 = 0.5 < 1$ (write-safe). ✔ Every multiplier is $\geq 1$ , so the design is manufacturable. ✔

Recall Solution

Read: $V_{Q}^{r e a d} = \frac{R _{P D}}{R _{P D} + R _{A C C}} = \frac{1}{1 + 1} = 0.5$ V $= V_{T H}$ → right on the tipping point → read upset risk. ✘ (zero margin, per the L3 "marginal" note) Write: $V_{Q}^{w r i t e} = \frac{R _{A C C}}{R _{A C C} + R _{P U}} = \frac{1}{1 + 4} = 0.2$ V $< 0.5$ → write got easier. ✔ So a stronger access helps write but hurts read — exactly the tension. The safe move is to keep access moderate and instead ensure $C R > 1$ by strengthening the pull-down.

Level 5 — Mastery

Recall Solution

Start from the read divider: $V_{Q}^{r e a d} = V_{D D} \cdot \frac{R _{P D}}{R _{P D} + R _{A C C}} \leq V_{T H}$ Let $r = R_{A C C} / R_{P D}$ . Divide numerator and denominator by $R_{P D}$ : $\frac{V _{D D}}{1 + r} \leq V_{T H} \Rightarrow 1 + r \geq \frac{V _{D D}}{V _{T H}} \Rightarrow r \geq \frac{V _{D D}}{V _{T H}} - 1$ Since $C R = R_{A C C} / R_{P D} = r$ , we need $C R \geq \frac{V _{D D}}{V _{T H}} - 1$ . Check L2.2: $V_{D D} = 1.0$ , $V_{T H} = 0.5$ → require $C R \geq 1.0/0.5 - 1 = 1$ . L2.2 had $C R = 4 \geq 1$ → safe, consistent with the $0.20$ V we found. ✔

Recall Solution

Write divider: $V_{Q}^{w r i t e} = V_{D D} \cdot \frac{R _{A C C}}{R _{A C C} + R _{P U}} \leq V_{T H}$ Let $s = R_{A C C} / R_{P U} = P R$ . Then $\frac{V _{D D} s}{s + 1} \leq V_{T H} \Rightarrow V_{D D} s \leq V_{T H} (s + 1) \Rightarrow s (V_{D D} - V_{T H}) \leq V_{T H}$ $P R = \frac{R _{A C C}}{R _{P U}} \leq \frac{V _{T H}}{V _{D D} - V _{T H}}$ The combined window (using $C R = R_{A C C} / R_{P D}$ and $P R = R_{A C C} / R_{P U}$ ): $read floor on C R \frac{V _{D D}}{V _{T H}} - 1 \leq C R, P R \leq write ceiling on P R \frac{V _{T H}}{V _{D D} - V _{T H}}$ Read pushes access to be weak relative to the pull-down; write pushes access to be strong relative to the pull-up. The design lives in the overlap — and shrinking $V_{D D}$ (or drifting $V_{T H}$ ) narrows it, which is why low-voltage SRAM is hard.

Recall Solution

Read floor: $\frac{V _{D D}}{V _{T H}} - 1 = \frac{1.0}{0.5} - 1 = 1.0$ . Need $C R \geq 1$ .
Write ceiling: $\frac{V _{T H}}{V _{D D} - V _{T H}} = \frac{0.5}{1.0 - 0.5} = 1.0$ . Need $P R \leq 1$ .
L4.1 design: $C R = R_{A C C} / R_{P D} = 2/1 = 2 \geq 1$ ✔ and $P R = R_{A C C} / R_{P U} = 2/4 = 0.5 \leq 1$ ✔. Inside both. ✔

Recall

Read-stability condition on the resistance ratio?

C R = \frac{R _{A C C}}{R _{P D}} \geq \frac{V _{D D}}{V _{T H}} - 1

, i.e. cell ratio

C R > 1

(pull-down stronger than access).

Write-success condition on the resistance ratio?

P R = \frac{R _{A C C}}{R _{P U}} \leq \frac{V _{T H}}{V _{D D} - V _{T H}}

, i.e.

P R < 1

(access stronger than the pull-up).

Why does widening only the access transistor threaten the read?

It lowers

R_{A C C}

, raising the read-divider voltage

V_{Q}

toward the trip point → read upset; helps write but hurts read.

In these SRAM margin formulas, what does

V_{T H}

mean?

The inverter's switching/trip point, not a single MOSFET's threshold voltage.

What does landing exactly at

V_{Q} = V_{T H}

mean physically?

Zero noise margin — the SNM square shrinks to a point, so any noise or transistor-variation flips the cell; never a safe design.