SRAM read - write operations: Foundations — Hardware deep dive

Before you can read the parent note, you need to earn every symbol it throws at you. We build them in the order they depend on each other: voltage → transistor → inverter → latch → the 6 transistors → the wires → the ratios.

1. Voltage, ground, and $V_{D D}$

Two special voltages appear everywhere:

Ground (often drawn as a downward "rake" symbol) = the zero reference, $0 V$ . This is "no push," which we read as logic 0.
$V_{D D}$ = the highest supply voltage the chip runs on (e.g. $1.0 V$ ). This is "full push," which we read as logic 1.

Figure 1 walkthrough. The red horizontal line at the top is the $V_{D D}$ rail — the "full push" level we read as logic 1. The black line at the bottom, with the shrinking-rungs symbol beneath it, is ground ( $0 V$ , logic 0). The double-headed arrow between them is voltage itself: the amount of push separating the two levels. Every signal in this whole page lives somewhere between these two lines.

2. The MOSFET — a voltage-controlled switch

There are two flavours, and the parent note uses both:

Type	Turns ON when gate is...	Good at pulling a node...
NMOS	HIGH ( $V_{D D}$ )	DOWN to $0$ (sinks current strongly)
PMOS	LOW ( $0$ )	UP to $V_{D D}$

Figure 2 walkthrough. Two transistor symbols side by side. On the left, the red NMOS: its gate wire enters from the left, and the red down-arrow shows what it is good at — dragging its node down toward ground (it turns on when the gate is HIGH). On the right, the black PMOS: the up-arrow shows it pulling its node up toward $V_{D D}$ (it turns on when the gate is LOW). The captions under each list the on-condition; note that each only conducts once its gate beats the threshold $V_{t}$ from §above.

3. W/L — how strong a transistor is

Formula Strength ↔ resistance (and where it holds)

When a transistor is ON and its drain-source voltage is small (the "linear" or "triode" regime, which is exactly the read/write tug-of-war situation), it acts like a resistor whose value is $R \approx \frac{1}{μ C _{o x} \frac{W}{L} ( V _{g s} - V _{t} )} \propto \frac{1}{W / L}$ Here $μ C_{o x}$ is a fixed process constant (set by the fabrication technology) and $(V_{g s} - V_{t})$ is how far the gate overdrives its threshold — both roughly the same for the transistors we compare, so only $W / L$ is left varying. This proportionality is a linear-regime, same-technology, same-overdrive approximation — it is not exact in saturation, but it is exactly the right mental model for comparing two on-transistors fighting over one node. So "M1 stronger than M5" and " $R_{M 1} < R_{M 5}$ " say the same thing.

4. The inverter — the switch that says "NO"

Figure 3 walkthrough. This is the inverter's transfer curve: input voltage on the horizontal axis, output voltage on the vertical axis. Read it left to right. When the input is low (left), the output sits high near $V_{D D}$ ; when the input is high (right), the output collapses to $0$ — that is the "opposite" behaviour. The steep drop in the middle is where the flip happens, and the red dashed cross-hair marks the exact input voltage where output = half — the trip point $V_{T H, in v}$ , here $0.5 V$ .

5. Cross-coupling → the latch → bistability

Figure 4 walkthrough. Two triangle symbols (inverters) point at each other. Follow the red wire: the top inverter's output — labelled $Q = 1$ — loops around and feeds the bottom inverter's input. The black wire does the mirror: the bottom inverter's output — labelled $\overline{Q} = 0$ — feeds back into the top inverter. Because each output drives the other's input, the two settle into a self-consistent locked pair; the caption underneath spells out that this mutual holding is what stores one bit.

6. The full symbol table (as used in the parent)

Now every symbol in the parent note has a home. Here is the complete list:

Prerequisite map

How to read this diagram. Each box is one foundation concept from this page. An arrow means "you need the box at the tail before you can understand the box at the head" — so read along the arrows from top to bottom. Start at the boxes with no incoming arrows (Voltage, W/L strength), follow the flow, and you will arrive at the parent topic in the bottom box. The map is your study order.

Equipment checklist

Test yourself — say the answer out loud before revealing.

What two voltage levels does the whole cell ever care about, and what logic values do they mean?

Near

0 V

= logic 0 (ground), near

V_{D D}

= logic 1.

Which terminal of a MOSFET decides if it conducts?

The gate — its voltage opens or closes the channel between source and drain.

What is the transistor threshold voltage

V_{t}

The gate-to-source voltage a MOSFET must beat before a channel forms and it turns ON; below it the device is OFF.

How does

V_{t}

differ from the inverter trip point

V_{T H, in v}

V_{t}

turns one transistor on;

V_{T H, in v}

is the input voltage at which a whole inverter flips its output.

NMOS is good at pulling a node which way; PMOS which way?

NMOS pulls DOWN toward 0 (strong sink); PMOS pulls UP toward

V_{D D}

Does a bigger

W / L

give more or less on-resistance, and in which regime does

R \propto 1/ (W / L)

hold?

Less resistance; the proportionality is a linear-regime, same-technology, same-overdrive approximation.

What does a CMOS inverter output for input 0 and input 1?

Output 1 for input 0; output 0 for input 1 (always the opposite).

What is the trip point

V_{T H, in v}

and why does it matter for reads?

The input voltage where the inverter flips its output; a read must keep

V_{Q}

below it or the cell flips (read upset).

Why does cross-coupling two inverters store a bit?

They settle in only two self-reinforcing states (

Q = 1, \overline{Q} = 0

Q = 0, \overline{Q} = 1

) — bistability, no refresh needed.

Why does

V_{Q} + V_{\overline{Q}} \approx V_{D D}

One node is pinned high (at

V_{D D}

) and the other pinned low (at

0

) by their inverters, so the two voltages add to the supply.

What do

B L

\overline{B L}

, and

W L

do?

B L

\overline{B L}

are the complementary data wires;

W L

turns on the access transistors to select the cell.

What is

Δ V

and who amplifies it?

The tiny bit-line voltage difference during a read; the sense amplifier amplifies it to a full logic level.

Which transistors are the access (pass) transistors and what type are they?

M5 and M6, both NMOS, gated by the word-line.

State the two sizing ratios and their required inequalities.

C R = (W / L)_{p d} / (W / L)_{a cc} > 1

for read stability;

P R = (W / L)_{p u} / (W / L)_{a cc} < 1

for write success.