SRAM read - write operations: Visual walkthrough — Hardware deep dive

What this page does: the parent note stated two sizing rules — one for reading, one for writing. Here we build both from scratch, one picture per step, without assuming any symbol in advance, until you can see why the access transistor is squeezed between two opposite demands. Start from a single transistor acting like a resistor; end with the full read/write stability window. (Every shorthand — $C R$ , $P R$ , $M 1$ , $M 2$ , $M 5$ , $V_{T H}$ — is defined the moment we first need it, below.)

This is the visual companion to SRAM read - write operations. If you have never met a CMOS inverter or MOSFET sizing (W/L), everything you need is built below.

Step 1 — A transistor is just a controllable resistor

WHY this first. Every "who wins the tug-of-war" argument on this page is really "which resistor is smaller?" So we must first agree that an on-transistor behaves like a resistor whose value depends on its size.

PICTURE.

The wider (bigger $W / L$ ) the transistor, the more current it passes, so the smaller its resistance. Read that sentence twice — it is the hinge of the whole page.

$W$ ::: channel width — how wide the conducting path is (wider = stronger).
$L$ ::: channel length — how far current must travel (longer = weaker).
$R \propto L / W$ ::: on-resistance shrinks as the transistor gets wider.

Step 2 — Two resistors in series make a voltage divider

WHY this tool. During both read and write, one internal node ( $Q$ ) is pulled up by one on-transistor and down by another at the same time. That is literally a divider. The voltage divider formula is the one tool that answers "where does the middle node settle?" — so we earn it now.

PICTURE.

Read the fraction physically: if the bottom resistor is tiny, the fraction is near $0$ → node sits low. If the bottom is huge, fraction near $1$ → node sits high. The bigger resistor wins the node toward its side. Hold that.

Step 3 — The trip point: when does an inverter change its mind?

WHY we need it. The whole danger of reading is that node $Q$ rises. "Rises to what, and is that dangerous?" only has meaning against a threshold. $V_{T H}$ is that finish line.

PICTURE.

Node held below $V_{T H}$ ::: safe, the inverter still reads the intended bit.
Node pushed above $V_{T H}$ ::: the fed inverter flips → data changes.

Step 4 — READ: the node that must NOT rise too far

WHY. This is Step 2 applied to real transistors. M5 is $R_{top}$ (pulling toward $V_{D D}$ ), M1 is $R_{bottom}$ (pulling to ground).

PICTURE.

To stay safe we need $V_{Q} < V_{T H}$ (Step 3). Look at the fraction: to make it small, we want $R_{M 1}$ small (strong pull-down) compared to $R_{M 5}$ . In size language — since a smaller resistance means a bigger $W / L$ (Step 1's mapping) — that is

$C R = \frac{( W / L ) _{pull-down}}{( W / L ) _{access}} > 1.$

$C R$ :: cell ratio — how much stronger (bigger $W / L$ ) the pull-down M1 is than the access M5.
$C R > 1$ :: pull-down dominates → $V_{Q}$ stays low → no read upset.

Step 5 — READ, the numbers (does the picture hold?)

WHY. A formula you can't put numbers into is a slogan. Let us verify.

PICTURE.

Take $V_{D D} = 1.0$ V, trip $V_{T H} = 0.5$ V, $R_{M 1} = 2 k Ω$ , $R_{M 5} = 6 k Ω$ :

$V_{Q} = 1.0 \cdot \frac{R _{M 1}}{R _{M 1} + R _{M 5}} = 1.0 \cdot \frac{2}{2 + 6} = 0.25 V < 0.5 V ✓$

The node meant to be "0" rises only to $0.25$ V — comfortably under the $0.5$ V finish line, so the latch never flips.

Why the cell ratio here is $3$ and not $1/3$ . By definition $C R = \frac{( W / L ) _{pull-down}}{( W / L ) _{access}}$ . Using Step 1's mapping "bigger $W / L$ ⇔ smaller $R$ ", each $W / L$ becomes $\propto 1/ R$ , so the ratio inverts when rewritten in resistances:

$C R = \frac{( W / L ) _{M 1}}{( W / L ) _{M 5}} = \frac{1/ R _{M 1}}{1/ R _{M 5}} = \frac{R _{M 5}}{R _{M 1}} = \frac{6}{2} = 3.$

So the pull-down is three times stronger — that is why $V_{Q}$ landed so low, and why the green safety band in the figure is wide.

Step 6 — WRITE: the SAME node must now be forced DOWN

WHY. Same tool (Step 2), opposite goal. Reading feared $Q$ rising; writing demands $Q$ falls below $V_{T H}$ .

PICTURE.

To make the fraction small (so $V_{Q}$ drops), we need $R_{M 5}$ small vs $R_{M 2}$ — i.e. access stronger than pull-up:

$P R = \frac{( W / L ) _{pull-up}}{( W / L ) _{access}} < 1.$

$P R$ :: pull-up ratio — how strong the pull-up M2 is relative to the access M5; we need it below $1$ .

Where does the " $1.2$ – $1.5 \times$ " number come from? $P R < 1$ only says "access must win by some margin." But real transistors are not perfect resistors, the trip point is not exactly $V_{D D} /2$ , and process/temperature vary. If access were only barely stronger, $V_{Q}$ would settle just below $V_{T H}$ and the tiniest wobble would abort the write. To keep $V_{Q}$ safely under the trip point across all corners, designers demand a comfort factor: the access transistor must be roughly $1.2$ – $1.5$ times stronger than the pull-up,

$\frac{( W / L ) _{access}}{( W / L ) _{pull-up}} ≳ 1.2 - 1.5.$

That factor is simply the safety cushion that turns the strict inequality $P R < 1$ into a reliable one. Notice the reversal: read wanted access weak (small $W / L$ ); write wants access strong (big $W / L$ ). Same transistor, opposite demands.

Step 7 — WRITE failure, the numbers (the degenerate case)

WHY. Every rule needs its failure shown, or you won't recognise it in an exam. This is the write's dark twin of Step 5.

PICTURE.

Same $V_{D D} = 1.0$ V, $V_{T H} = 0.5$ V, but a monster PMOS $R_{M 2} = 1 k Ω$ , access $R_{M 5} = 6 k Ω$ , writing $B L = 0$ :

$V_{Q} = 1.0 \cdot \frac{R _{M 5}}{R _{M 5} + R _{M 2}} = 1.0 \cdot \frac{6}{6 + 1} = 0.86 V > 0.5 V ✗ write fails$

We needed $V_{Q} < 0.5$ V; the strong pull-up pinned it at $0.86$ V. Fix: shrink the PMOS (raise $R_{M 2}$ ) or widen access (lower $R_{M 5}$ ) until the fraction drops. The red band in the figure is the forbidden zone — $V_{Q}$ landed inside it.

Step 8 — The squeeze: both rules at once

WHY. This single window is the entire exam and the entire art of SRAM sizing. Everything above collapses to it.

PICTURE.

The one-picture summary

One node, $Q$ , watched twice. In read it is a divider between access M5 (top) and pull-down M1 (bottom) and must stay below $V_{T H}$ → pull-down wins → $C R > 1$ . In write it is a divider between access M5 (bottom) and pull-up M2 (top) and must drop below $V_{T H}$ → access wins → access $≳ 1.2$ – $1.5 \times$ pull-up. Same divider, mirrored demands, one squeezed access transistor.

Recall Feynman retelling of the whole walkthrough

Every on-transistor is just a resistor whose size sets how small the resistance is — bigger $W / L$ means smaller $R$ (Step 1). Whenever one resistor pulls a node up and another pulls it down, the node lands at a spot decided by their ratio — the bigger resistor drags the node toward its own side (Step 2). An inverter has a tipping voltage $V_{T H}$ : cross it and it flips (Step 3). Reading: the "0" node $Q$ gets tugged upward by the bit-line through access transistor M5; the pull-down M1 must be the beefier resistor so the node stays under the tipping voltage — $0.25$ V in our numbers, safe, and that "3-times-stronger" is the cell ratio (Steps 4–5). Make access too big and you tip it — read upset. Writing: now we want to tip it, so M5 must out-muscle the PMOS pull-up M2 and drag the node below the tip; with a monster PMOS it only fell to $0.86$ V and the write flopped (Steps 6–7). We insist access be $1.2$ – $1.5 \times$ stronger than the pull-up just to keep a safety cushion. So read wants access weak, write wants access strong — the access transistor lives in a narrow window between the two, and that window is the whole story (Step 8).

Recall

In the read divider, which resistor sits on top pulling $Q$ up? ::: The access transistor M5 (bit-line side).
In the write divider, which resistor is on top? ::: The PMOS pull-up M2.
Why must $C R > 1$ ? ::: So the pull-down M1 (small $R$ ) dominates and keeps $V_{Q}$ below $V_{T H}$ during read.
Read example $V_{Q}$ with $R_{M 1} = 2 k, R_{M 5} = 6 k, V_{D D} = 1$ ? ::: $0.25$ V — safe.
Write-fail $V_{Q}$ with $R_{M 5} = 6 k, R_{M 2} = 1 k$ ? ::: $0.86$ V — above trip, write fails.
Where does the $1.2$ – $1.5$ write factor come from? ::: A safety cushion turning $P R < 1$ into a reliable margin against process/temperature/trip-point variation.