SRAM read - write operations: Worked examples — Hardware deep dive

This page hunts down every case an SRAM read/write problem can throw at you. Before we start, remember the two numbers that decide everything (built in the parent note):

Cell ratio $C R = \frac{( W / L ) _{pull-down}}{( W / L ) _{access}}$ — governs whether a read stays safe.

Pull-up ratio $P R = \frac{( W / L ) _{pull-up}}{( W / L ) _{access}}$ — governs whether a write succeeds.

Everything below is just plugging real numbers into these two ideas. If a symbol here feels new, it was earned in the parent note — glance back, then continue.

Definition Design margins used on this page (fixed once, used everywhere)

To turn " $C R > 1$ " and " $P R < 1$ " into concrete pass/fail tests, this page adopts one global specification — the same rules every numeric example uses:

Read-margin rule: $C R = \frac{( W / L ) _{pull-down}}{( W / L ) _{access}} \geq 1.2$ . WHY $1.2$ and not just $> 1$ : $C R = 1$ is the exact cliff (Ex 3); real cells need headroom against noise (see Static Noise Margin (SNM)), so we demand at least 20% margin.
Write-margin rule: the access-vs-pull-up strength ratio $\frac{( W / L ) _{access}}{( W / L ) _{pull-up}} \geq 1.2$ (equivalently $P R \leq 1/1.2 \approx 0.83$ ). WHY: the access transistor must overpower the PMOS pull-up with margin, not merely tie it.

These two numbers ( $\geq 1.2$ for read, $\geq 1.2$ for write) are the spec for Ex 4, 8 and 9. Ex 9 deliberately tightens the write rule to $\geq 1.5$ inside its own statement to show a harsher exam variant — it will say so explicitly.

$V_{node} = V_{D D} \cdot \frac{R _{bottom}}{R _{top} + R _{bottom}}$

where $R_{bottom}$ is the transistor pulling toward ground (0 V) and $R_{top}$ is the transistor pulling toward $V_{D D}$ . We will use this single formula in every example. Read it as: "the node sits closer to whichever resistor is smaller." The figure below is the picture to keep in your head for all eleven examples.

Look at the figure: the yellow NODE dot is the internal storage node ( $Q$ or $\overline{Q}$ ). The pink $R_{top}$ (pulls to $V_{D D}$ ) and blue $R_{bottom}$ (pulls to ground) are the two "on" transistors fighting over it. Every example just swaps which transistor plays top and bottom, and what voltage each end pulls toward.

The scenario matrix

Every SRAM read/write question is one (or a mix) of these cells:

#	Case class	What's being tested	Example
A	Read, safe ( $C R > 1$ )	node stays below trip, no upset	Ex 1
B	Read, upset ( $C R < 1$ )	node rises above trip, data lost	Ex 2
C	Read, boundary ( $V_{Q} = V_{T H}$ )	the exact tipping point	Ex 3
D	Write, success (access beats pull-up)	node forced below trip	Ex 4
E	Write, failure (pull-up too strong)	node stuck above trip	Ex 5
F	Degenerate: WL off	access transistors open → hold mode	Ex 6
G	Which bit-line droops (sign/direction)	reading the correct bit	Ex 7
H	Real-world sizing (word problem)	pick $(W / L)$ to satisfy both constraints	Ex 8
I	Exam twist: both must hold	find the access-width window	Ex 9
J	Limiting case ( $R_{A C C} \to \infty$ or $0$ )	what happens at the extremes	Ex 10
K	Write boundary ( $P R = 1$ )	the exact write tipping point	Ex 11

Because "strength" of a MOSFET rises with $W / L$ and its on-resistance falls with $W / L$ , we freely translate between "stronger transistor" ⇄ "smaller resistance". See MOSFET sizing (W/L) for why $R \propto L / W$ .

Fixed constants for all numeric examples unless stated otherwise: $V_{D D} = 1.0 V$ , inverter trip point $V_{T H} = 0.5 V$ .

Case A — Read, safe

Worked example Ex 1 — Comfortable read (cell A)

Cell stores $Q = 0$ . On read, $B L$ is pre-charged to $V_{D D} = 1.0$ V, WL asserted. Model pull-down M1 as $R_{P D} = 2 k Ω$ and access M5 as $R_{A C C} = 8 k Ω$ . Find $V_{Q}$ and decide: upset or safe?

Forecast: M5 tries to lift $Q$ toward $B L = 1.0$ V; M1 pins it to ground. Which wins? Guess before reading.

Identify the tug-of-war. Top resistor = M5 (to $B L \approx V_{D D}$ ), bottom = M1 (to ground). Why this step? The stored 0 sits between these two "on" transistors; the divider tells us the disturbed node voltage.
Apply the divider. The node leans toward ground by the fraction of the bottom resistor: $V_{Q} = V_{D D} \cdot \frac{R _{P D}}{R _{P D} + R _{A C C}} = 1.0 \cdot \frac{2}{2 + 8} = 0.20 V$ Why this step? $R_{P D}$ is the resistor pulling to ground; its share of the total sets how low $Q$ stays.
Compare to trip. $0.20 < 0.5 \Rightarrow$ the other inverter never flips → safe read. Why this step? $V_{T H}$ is the border between "still a 0" and "flipped to 1"; see Static Noise Margin (SNM).

Verify: $C R = R_{A C C} / R_{P D} = 8/2 = 4 > 1$ ✔ (pull-down is 4× stronger). Units: kΩ cancel in the ratio; volts × dimensionless = volts. Sanity: bottom resistor is small, so node hugs ground — matches $0.20$ V. ✔

Case B — Read, upset

Worked example Ex 2 — Read destroys the bit (cell B)

Same read as Ex 1 but a badly sized cell: $R_{P D} = 6 k Ω$ (weak pull-down), $R_{A C C} = 2 k Ω$ (strong access). Find $V_{Q}$ ; does it survive?

Forecast: Now the access is the small resistance. Which way does $Q$ get dragged?

Same divider, new numbers. $V_{Q} = 1.0 \cdot \frac{R _{P D}}{R _{P D} + R _{A C C}} = 1.0 \cdot \frac{6}{6 + 2} = 0.75 V$ Why this step? Identical physics; only the resistances changed, so we reuse the divider.
Compare to trip. $0.75 > 0.5$ → node $Q$ has risen above the trip point → the opposite inverter starts turning → read upset, data destroyed. Why this step? Crossing $V_{T H}$ is the definition of the latch tipping.

Verify: $C R = 2/6 = 0.33 < 1$ ✔ — the parent's rule $C R > 1$ is violated, and indeed we got upset. The two independent methods (voltage vs. $C R$ ) agree. ✔

Case C — Read, exact boundary

Worked example Ex 3 — The knife's edge (cell C)

Keep $R_{P D} = 2 k Ω$ . What access resistance $R_{A C C}$ puts $V_{Q}$ exactly at the trip point $0.5$ V (the moment of imminent upset)?

Forecast: The threshold sits at half of $V_{D D}$ . What does that force the two resistors to be?

Set the divider equal to trip. $0.5 = 1.0 \cdot \frac{2}{2 + R _{A C C}}$ Why this step? We solve for the resistance that lands the node precisely on the border.
Solve. $0.5 (2 + R_{A C C}) = 2 \Rightarrow 1 + 0.5 R_{A C C} = 2 \Rightarrow R_{A C C} = 2 k Ω$ . Why this step? Straight algebra to isolate $R_{A C C}$ .
Interpret. At $R_{A C C} = R_{P D}$ , i.e. $C R = 1$ , the node sits at half rail. Any weaker pull-down ( $C R < 1$ ) tips into upset (Case B); any stronger ( $C R > 1$ ) is safe (Case A). Our read-margin rule ( $C R \geq 1.2$ ) sits safely to the right of this cliff. Why this step? This is why the parent insists on $C R > 1$ with margin — $C R = 1$ is the cliff edge.

Verify: $C R = R_{A C C} / R_{P D} = 2/2 = 1$ exactly ✔. Plug back: $1.0 \cdot \frac{2}{2 + 2} = 0.5$ V = $V_{T H}$ ✔.

Case D — Write, success

Worked example Ex 4 — A clean write (cell D)

Cell holds $Q = 1$ ; we write 0 by driving $B L = 0$ . During the flip, node $Q$ is a divider between access M5 (to $B L = 0$ , i.e. ground) and PMOS pull-up M2 (to $V_{D D}$ ). Sizes: $R_{A C C} = 3 k Ω$ , $R_{P U} = 9 k Ω$ . Find $V_{Q}$ ; does it flip, and does it meet the write-margin rule?

Forecast: To write 0 we need $Q$ below trip. Access is the small resistor here — good sign?

Set up the divider — mind the ends. The access transistor now pulls toward $B L = 0$ (ground), so it is the bottom resistor; the PMOS pull-up pulls toward $V_{D D}$ , so it is the top resistor. Our master formula uses the bottom resistor (the one to ground), which here is the access: $V_{Q} = V_{D D} \cdot \frac{R _{bottom}}{R _{top} + R _{bottom}} = V_{D D} \cdot \frac{R _{A C C}}{R _{P U} + R _{A C C}} = 1.0 \cdot \frac{3}{9 + 3} = 0.25 V$ Why this step? The node leans toward whichever end has the smaller resistor; here the access (to ground) is small, so the node is dragged low.
Compare to trip. $0.25 < 0.5 \Rightarrow Q$ dropped below trip → the opposite inverter flips $\overline{Q}$ high → cross-coupling latches the new $Q = 0$ . Write succeeds. Why this step? Crossing below $V_{T H}$ triggers the regenerative flip described in the parent.
Check the write-margin rule. The rule is stated in $(W / L)$ : access must beat pull-up, $\frac{( W / L ) _{access}}{( W / L ) _{pull-up}} \geq 1.2$ . Since $R \propto 1/ (W / L)$ , this ratio equals $\frac{R _{P U}}{R _{A C C}} = \frac{9}{3} = 3$ . Why this step? Converting the sizing rule into resistances so we can test it with the numbers we have.

Verify: $P R = \frac{( W / L ) _{pull-up}}{( W / L ) _{access}} = \frac{R _{A C C}}{R _{P U}} = \frac{3}{9} = 0.33$ . Global write-margin needs $P R \leq 1/1.2 \approx 0.83$ : since $0.33 \leq 0.83$ ✔ (and also $< 1$ ). Strength ratio $\frac{( W / L ) _{access}}{( W / L ) _{pull-up}} = \frac{R _{P U}}{R _{A C C}} = 3 \geq 1.2$ ✔ — comfortably meets the global write-margin. ✔

Case E — Write, failure

Worked example Ex 5 — Write can't win (cell E)

Same write attempt, but a fat PMOS pull-up: $R_{P U} = 1 k Ω$ , access $R_{A C C} = 6 k Ω$ . Find $V_{Q}$ ; does the write take?

Forecast: Now the pull-up is the small resistance. Who wins the tug?

Divider again. Access ( $R_{A C C}$ ) is the bottom resistor (to $B L = 0$ ), pull-up ( $R_{P U}$ ) is the top (to $V_{D D}$ ): $V_{Q} = 1.0 \cdot \frac{R _{A C C}}{R _{P U} + R _{A C C}} = 1.0 \cdot \frac{6}{1 + 6} = 0.857 V$ Why this step? Same node, same physics; the strong (small-R) pull-up keeps $Q$ high.
Compare to trip. $0.857 > 0.5 \Rightarrow Q$ never fell below trip → latch holds → write fails. Why this step? No crossing of $V_{T H}$ means no regenerative flip.
Fix. Shrink the PMOS (raise $R_{P U}$ ) or widen the access (lower $R_{A C C}$ ) until $V_{Q} < 0.5$ . Why this step? This is the parent's write-margin rule made concrete.

Verify: strength ratio $\frac{( W / L ) _{access}}{( W / L ) _{pull-up}} = \frac{R _{P U}}{R _{A C C}} = \frac{1}{6} = 0.17 < 1.2$ → violates the write-margin rule ✔, consistent with the failure. This example's own $V_{Q} = 6/7 \approx 0.857$ V matches the parent note's Ex 3 write-fail number. ✔

Case F — Degenerate: word-line off

Worked example Ex 6 — Hold mode (cell F)

Neither read nor write: WL = 0, so both access transistors M5 and M6 are OFF (approximate their resistance as $R_{A C C} \to \infty$ ). Cell holds $Q = 0$ . What is $V_{Q}$ , and can bit-line noise flip it?

Forecast: With the access transistor cut off, is the node connected to the bit-line at all?

Open the top resistor. In the read divider, $R_{A C C}$ is the top resistor; let $R_{A C C} \to \infty$ : $V_{Q} = V_{D D} \cdot lim_{R_{A C C} \to \infty} \frac{R _{P D}}{R _{P D} + R _{A C C}} = V_{D D} \cdot 0 = 0 V$ Why this step? An infinite series resistor passes no current; the node is pulled fully to whatever the inner inverter sets — here, ground.
Conclude. $Q$ sits at a clean 0 V, fully restored by its own inverter; bit-line activity can't reach it. This is why SRAM holds without refresh (contrast DRAM read-write operations). Why this step? It shows the "static" in SRAM: hold mode is the safest state.

Verify: limit is $0$ ✔. Sanity: with WL off the cell is just two inverters looping — the parent's bistable latch. ✔

Case G — Which bit-line droops (sign/direction)

Worked example Ex 7 — Reading the right bit (cell G)

Cell stores $Q = 1, \overline{Q} = 0$ . Both bit-lines pre-charged to $V_{D D}$ , WL on. Which line droops, and what does the sense amp report?

Forecast: Only a node at 0 can sink current and pull its line down. Which node is that?

Match nodes to lines. Recall from the parent's 6T cell that the two access transistors are M5 (connecting $Q \to B L$ ) and M6 (connecting $\overline{Q} \to \overline{B L}$ ) — M6 is simply the mirror-image partner of M5 on the complementary side. Why this step? Direction depends on which internal node is low and which line it reaches.
Find the low node. $\overline{Q} = 0$ → it sinks current through M6 → $\overline{B L}$ droops below $V_{D D}$ . $Q = 1$ can't pull $B L$ below $V_{D D}$ . Why this step? An NMOS pull-down sinks (pulls down) but never sources above rail.
Read the sign. $Δ V = V_{B L} - V_{\overline{B L}} > 0$ . A positive $Δ V$ → sense amp latches a logic 1, matching the stored bit. Why this step? The sign of the difference is the decoded bit.

Verify: stored $Q = 1$ → read reports $1$ ✔ (consistent, non-destructive). Symmetric check: if $Q = 0$ , then $B L$ droops, $Δ V < 0$ , reads 0. Both signs covered. ✔

Case H — Real-world sizing (word problem)

Worked example Ex 8 — Design a cell that reads safely (cell H)

A designer fixes the access transistor at $(W / L)_{access} = 1$ . The read-margin rule demands $C R \geq 1.2$ . What minimum $(W / L)_{pull-down}$ satisfies this, and what is $V_{Q}$ on a read if $R \propto 1/ (W / L)$ and the access has $R_{A C C} = 6 k Ω$ ?

Forecast: $C R \geq 1.2$ means pull-down at least 1.2× wider. Guess the resulting node voltage — under half rail?

Apply the read-margin rule. $C R = \frac{( W / L ) _{P D}}{( W / L ) _{A C C}} \geq 1.2 \Rightarrow (W / L)_{P D} \geq 1.2 \times 1 = 1.2$ . Why this step? Directly enforces the global read-margin spec.
Translate to resistance. $R \propto 1/ (W / L)$ , so with access $= 6 k Ω$ at $(W / L) = 1$ , a pull-down of $(W / L) = 1.2$ has $R_{P D} = 6/1.2 = 5 k Ω$ . Why this step? We need resistances to compute the node voltage.
Node voltage on read. $V_{Q} = 1.0 \cdot \frac{R _{P D}}{R _{P D} + R _{A C C}} = 1.0 \cdot \frac{5}{5 + 6} = 0.455 V$ Why this step? Confirms the spec actually keeps $V_{Q} < 0.5$ .

Verify: $0.455 < 0.5$ ✔ safe (thin margin — exactly what "minimum spec" means). $C R = R_{A C C} / R_{P D} = 6/5 = 1.2$ ✔ meets minimum exactly. Relevant to Cache memory where dense cells push $C R$ to its floor. ✔

Case I — Exam twist: both constraints at once

Worked example Ex 9 — The access-width window (cell I)

Fix pull-down at $(W / L)_{P D} = 2$ and PMOS pull-up at $(W / L)_{P U} = 1$ . This harsher exam variant tightens the write rule: read needs $C R \geq 1.2$ (global rule), but write now needs strength ratio $\frac{( W / L ) _{A C C}}{( W / L ) _{P U}} \geq 1.5$ . Find the allowed range of $(W / L)_{A C C}$ .

Forecast: Read caps the access from above; write pushes it from below. Is there a window that satisfies both?

Read (upper bound). $C R = \frac{2}{( W / L ) _{A C C}} \geq 1.2 \Rightarrow (W / L)_{A C C} \leq \frac{2}{1.2} = 1.667$ . Why this step? Access must stay weak enough not to upset the read → an upper limit.
Write (lower bound). $\frac{( W / L ) _{A C C}}{1} \geq 1.5 \Rightarrow (W / L)_{A C C} \geq 1.5$ . Why this step? Access must beat the pull-up with the tighter 1.5× margin → a lower limit.
Intersect. $1.5 \leq (W / L)_{A C C} \leq 1.667$ . A narrow but non-empty window exists — this squeeze is the SRAM sizing tension from the parent note. Why this step? Both constraints must hold simultaneously; only the overlap is legal.

Verify: $1.5 \leq 1.667$ ✔ (window non-empty). Check endpoints: at $1.5$ , write ratio $= 1.5 \geq 1.5$ ✔ and $C R = 2/1.5 = 1.33 \geq 1.2$ ✔; at $1.667$ , $C R = 1.2$ ✔ and write ratio $= 1.667 \geq 1.5$ ✔. Both ends legal. ✔

Case J — Limiting case

Worked example Ex 10 — Push access resistance to the extremes (cell J)

Take the read divider with $R_{P D} = 2 k Ω$ . Evaluate $V_{Q}$ as (a) $R_{A C C} \to \infty$ and (b) $R_{A C C} \to 0$ . What do these limits mean physically?

Forecast: One extreme is "no connection", the other is "wire". Which causes upset?

Limit (a): $R_{A C C} \to \infty$ . $V_{Q} = lim_{R_{A C C} \to \infty} 1.0 \cdot \frac{2}{2 + R _{A C C}} = 0 V$ Why this step? As the top resistor grows without bound, its share of the divider vanishes, so the node is dragged fully to the bottom end (ground) — access effectively OFF, node fully restored to 0 → safest possible read (but no signal reaches the bit-line, so infinitely slow).
Limit (b): $R_{A C C} \to 0$ . $V_{Q} = lim_{R_{A C C} \to 0} 1.0 \cdot \frac{2}{2 + R _{A C C}} = 1.0 \cdot \frac{2}{2 + 0} = 1.0 V = V_{D D}$ Why this step? When the access resistance collapses to zero it becomes a perfect wire, so the bit-line (sitting at $V_{D D}$ ) shorts straight onto node $Q$ ; the divider has no "bottom share" left to pull the node down, and it is slammed to the full rail. Since $1.0 > 0.5 = V_{T H}$ , this guarantees read upset — the worst case.
Trade-off. Speed grows as $R_{A C C}$ shrinks, but stability collapses. The usable design sits between these extremes — the finite window of Ex 9. Why this step? It frames every earlier example as a point on this continuum.

Verify: (a) limit $= 0$ ✔; (b) limit $= 1.0 = V_{D D}$ ✔; and $1.0 > 0.5 = V_{T H}$ confirms the short-circuit case upsets ✔.

Case K — Write, exact boundary

Worked example Ex 11 — The write knife's edge (cell K)

Writing $B L = 0$ into a cell holding $Q = 1$ . Access $R_{A C C} = 4 k Ω$ . What pull-up resistance $R_{P U}$ places node $Q$ exactly at the trip point $0.5$ V — the precise write tipping point? What is $P R$ there?

Forecast: By analogy with the read boundary (Ex 3, $C R = 1$ ), guess: does the write boundary land at $P R = 1$ ?

Set the write divider equal to trip. Access is the bottom resistor (to $B L = 0$ ), pull-up the top (to $V_{D D}$ ): $0.5 = 1.0 \cdot \frac{R _{A C C}}{R _{P U} + R _{A C C}} = \frac{4}{R _{P U} + 4}$ Why this step? We solve for the pull-up that lands $Q$ precisely on the write border.
Solve. $0.5 (R_{P U} + 4) = 4 \Rightarrow R_{P U} + 4 = 8 \Rightarrow R_{P U} = 4 k Ω$ . Why this step? Straight algebra to isolate $R_{P U}$ .
Interpret. At $R_{P U} = R_{A C C}$ , node sits at half rail. In $(W / L)$ terms this is $P R = \frac{( W / L ) _{P U}}{( W / L ) _{A C C}} = \frac{R _{A C C}}{R _{P U}} = 1$ : the write cliff. Any weaker pull-up ( $R_{P U} > R_{A C C}$ , i.e. $P R < 1$ ) pushes $V_{Q}$ below trip → write succeeds (Case D). Any stronger pull-up ( $P R > 1$ ) holds $V_{Q}$ above trip → write fails (Case E). This is the exact mirror of the read boundary in Ex 3. Why this step? It pins down why the parent insists on $P R < 1$ — $P R = 1$ is the write cliff, just as $C R = 1$ is the read cliff.

Verify: $P R = R_{A C C} / R_{P U} = 4/4 = 1$ exactly ✔. Plug back: $1.0 \cdot \frac{4}{4 + 4} = 0.5$ V $= V_{T H}$ ✔. Symmetry check: read cliff was $C R = 1$ (Ex 3), write cliff is $P R = 1$ — both at half rail. ✔

Recall Recall check

In a read, is the node dragged toward the smaller or larger of its two resistances? ::: Toward the smaller resistance (that transistor wins the tug-of-war). What single comparison decides upset vs. safe read? ::: Whether the disturbed node voltage $V_{Q}$ is below (safe) or above (upset) the trip point $V_{T H}$ . Where is the read cliff and where is the write cliff? ::: Read cliff at $C R = 1$ (Ex 3), write cliff at $P R = 1$ (Ex 11); both put the node exactly at half rail. Why does Ex 9 produce a window rather than a single value? ::: Read imposes an upper bound on access strength, write imposes a lower bound; only their overlap is legal.