Question bank — SRAM read - write operations

False. The cross-coupled latch is actively powered and continuously restores its own state, so nothing decays and no rewrite is needed — provided $CR>1$ so the read disturbance never trips it.

False. Current flowing in from the pre-charged bit-line through the access transistor lifts that node to a small $V_Q>0$; the design only guarantees $V_Q$ stays below the inverter trip point, not zero.

True. Pre-charge doesn't know the data; both $BL,\overline{BL}$ go to $V_{DD}$, then float, and the cell pulls one down. Downward sensing is robust because the NMOS pull-down sinks current well.

False. It helps writes but hurts reads — a strong access transistor injects more current into the "0" node, raising $V_Q$ toward the trip point and risking read upset. It's a squeeze, not a free win.

False. You drive both lines complementarily ($BL=0,\overline{BL}=V_{DD}$); forcing both sides lets the cross-coupling regenerate the new state instead of leaving a marginal, possibly-not-flipped cell.

True. Read wants access weak vs pull-down ($CR>1$); write wants access strong vs pull-up ($PR<1$). The single access transistor must satisfy both simultaneously — that trade-off is SRAM sizing.

False. A strong pull-up firmly resists being overwritten — it holds $V_Q$ up during a write and can cause write failure. Pull-ups are deliberately kept the weakest device.

True. WL gates the access transistors M5/M6; asserting it connects $Q,\overline{Q}$ to the bit-lines. The bit-line drive/sensing then decides whether it's a read or a write.

False. $CR=1$ means access and pull-down are equally strong, so $V_Q$ rises to roughly half $V_{DD}$ — right at the danger zone. You need $CR>1$ (typically 1.2–2) with margin, or noise pushes it over the trip point.

Reading works the other way: bit-lines are already pre-charged high, and the cell only needs to sink current to pull one down. We rely on strong NMOS sinking, not weak PMOS sourcing.

It's inverted. $CR=(W/L{)}_{\text{pull-down}}/(W/L{)}_{\text{access}}$, and we want it >1 so the pull-down out-muscles the access transistor and keeps $V_Q$ low.

The PMOS pulls toward $V_{DD}$; it's the enemy of the write. The access transistor (via $BL=0$) must pull the node below the trip point against the PMOS.

Upset happens on the stored-0 node: current from the high bit-line lifts $V_Q$ up above the trip point. It's an unwanted rise on the low node, not a fall on the high node.

It matters critically. The access transistor is the device that must conduct the bit-line's 0 into the node and overpower the pull-up ($PR<1$). A weak access transistor can't win even with $BL=0$.

$\Delta V$ is the useful signal the sense amplifier needs; it develops on the bit-line being pulled down. Disturbance is measured by the internal node $V_Q$ rise, a separate quantity — a healthy read has good $\Delta V$ and small $V_Q$.

Because the pull-down NMOS sinks current strongly and reliably, so letting the cell drag a high line down is robust; asking a weak PMOS to source a low line up would be slower and noisier.

Read needs it weak (vs pull-down, $CR>1$) to avoid disturbing; write needs it strong (vs pull-up, $PR<1$) to force a flip. One device can't be both simultaneously — hence a compromise "sweet spot" governed by W/L sizing.

It must not hold the node up so stubbornly that a write fails, and reads never rely on it to source current. Weak pull-up eases writes while the actively-latched pair still holds data fine.

Crossing the trip point flips the other inverter's output, which is cross-coupled back to reinforce the new value on the first node — a positive-feedback loop (bistability of the inverter pair) that snaps the cell fully into the new state.

Differential sensing cancels common-mode noise and needs only a tiny $\Delta V$, letting the sense amplifier decide fast and correctly even before either line swings to a full logic level.

SNM is the largest noise voltage the latch can tolerate before flipping; the read-time $V_Q$ rise eats into that margin. Sizing for $CR>1$ keeps the disturbance well inside the SNM.

SRAM stores the bit as a stable powered state of the latch, not as charge on a capacitor. Nothing leaks away, so the value persists as long as power is on.

The bit-lines sit at whatever leftover/leakage voltage they had, so the sense amp gets an undefined or wrong $\Delta V$ — the read result is unreliable even in a perfectly sized cell.

You pull both internal nodes down; the complementary-restoring feedback has nothing to latch onto, leaving the cell in an undefined/contended state — it's why writes must drive complementary values.

The cell stays connected to the floating bit-lines, prolonging the read disturbance and blocking a clean pre-charge for the next access — $V_Q$ can drift toward the trip point, risking a delayed upset.

Reads fail: $V_Q$ rises above the trip point and the cell flips (read upset). Writes may work fine, but you've traded away data integrity — unacceptable for a memory.

Reads are safe (low disturbance) but writes may still be marginal if the access transistor is too weak to swing the node — you must check both ratios, not just one.

The trip point and SNM shrink, so the same $V_Q$ disturbance becomes a larger fraction of the margin — read upset and write failure both worsen, which is why low-voltage SRAM needs careful re-sizing or assist circuits.