Memory Technologies

Question 1 (15)

(a) Even distribution: $t = \dfrac{64\text{ ms}}{8192} = 7.8125\ \mu\text{s}$. (3)

• Correct division (2), value with units (1).

(b) Total refresh time per window $= 8192 \times 75\text{ ns} = 614{,}400\text{ ns} = 0.6144\text{ ms}$. Overhead $= \dfrac{0.6144}{64} = 0.0096 = 0.96\%$. (4)

• Total refresh time (2), ratio (1), percentage (1).

(c) $t_{ret}\propto C$. Halving $C$ halves $t_{ret}$: new $t_{ret}=32\text{ ms}$. The same 8192 rows must now be refreshed twice as often, so refresh time per window is unchanged per window but windows are half as long → overhead doubles to $1.92\%$. (5)

• $t_{ret}=32$ ms (2), reasoning overhead doubles (2), value $1.92\%$ (1).

(d) Any valid: e.g. Per-bank / distributed refresh or temperature-compensated refresh (extending interval at low temp) or bank-grouping so other banks serve requests during a bank's refresh. Why: it overlaps refresh with useful access / reduces number/frequency of forced-idle refreshes. (3)

Question 2 (14)

(a) During read, the access transistor forms a voltage divider between the pre-charged bitline (pulling the '0' node up) and the driver transistor (pulling it down). If the '0' node rises above the switching threshold of the opposite inverter, the cross-coupled feedback can regeneratively flip the state. The robustness metric is the Static Noise Margin (SNM) (read SNM). (4)

• Divider/disturb mechanism (2), regenerative flip (1), SNM named (1).

(b) $t=\dfrac{C\,\Delta V}{I}=\dfrac{200\text{ fF}\times 100\text{ mV}}{40\ \mu\text{A}}=\dfrac{200\times10^{-15}\times0.1}{40\times10^{-6}}$ $=\dfrac{2\times10^{-14}}{4\times10^{-5}}=5\times10^{-10}\text{ s}=0.5\text{ ns}$. (5)

• Formula (2), substitution (2), $0.5$ ns (1).

(c) Wider access transistor increases read current (faster) but also strengthens its pull-up effect on the '0' storage node, raising that node's voltage during read → lower cell ratio $\beta$ (driver-to-access strength) → reduced read SNM → higher probability of read-disturb flip. It is a speed-vs-stability trade-off. (5)

• Faster read (1), raises '0' node (2), cell ratio & SNM degrade (2).

Question 3 (16)

(a) TLC = 3 bits → $2^3 = 8$ levels; distinguishing 8 levels needs $8-1 = 7$ read reference voltages. (3)

(b) TLC: $\dfrac{4.0}{8-1}=\dfrac{4.0}{7}=0.571\text{ V}$ between adjacent centers. MLC (4 levels): $\dfrac{4.0}{4-1}=\dfrac{4.0}{3}=1.333\text{ V}$. MLC spacing is $\approx 2.33\times$ wider, giving much larger margin. (4)

• TLC $0.571$ V (2), MLC $1.333$ V (1), comparison (1).

(c) Total bytes that can be written = $256\text{ GB}\times 3000 = 768{,}000\text{ GB}$ (host-visible endurance before WAF). Effective daily flash writes $= 40\text{ GB}\times 3.2 = 128\text{ GB/day}$. Flash write budget $= 256\times3000 = 768{,}000\text{ GB}$. Lifetime $=\dfrac{768{,}000}{128}=6000\text{ days}=\dfrac{6000}{365}\approx 16.4\text{ years}$. (6)

• WAF applied (2), total budget (2), days→years (2).

(d) TLC packs 8 levels in the same threshold window, so voltage margins between levels are much smaller; oxide degradation and trapped charge from cycling shift thresholds enough to cross narrower margins far sooner, so fewer P/E cycles are tolerated. (3)

Question 4 (16)

(a) Transfers/s $= 1600\times10^6 \times 2 = 3.2\times10^9$ (DDR). Bandwidth $= 3.2\times10^9 \times 8\text{ bytes} = 25.6\times10^9\text{ B/s}=25.6\text{ GB/s}$. (4)

• DDR doubling (2), ×8 bytes (1), value (1).

(b) Clock period $=\dfrac{1}{1600\text{ MHz}}=0.625\text{ ns}$. $t_{CL}=22\times0.625=13.75\text{ ns}$. (3)

(c) $t_{RCD}+t_{CL}=(22+22)\times0.625=44\times0.625=27.5\text{ ns}$. Burst of 8 transfers, each half a cycle $=8\times\dfrac{0.625}{2}=8\times0.3125=2.5\text{ ns}$. Total $=27.5+2.5=30.0\text{ ns}$. (5)

• RCD+CL (2), burst time (2), total (1).

(d) $\lceil 50/25.6\rceil = \lceil1.95\rceil = 2$ channels. (2) Real sustained falls short because of refresh cycles, bank/row activation overhead, read-write bus turnaround, and access-pattern non-idealities that prevent 100% bus utilization. (2)

Question 5 (14)

(a) SEC Hamming needs $2^k \ge n+k+1$ with $n=64$. $k=7$: $128 \ge 72$ ✓ (and $k=6$: $64\ge71$ ✗). So SEC needs 7 check bits. SECDED adds one overall parity bit → 8 check bits, total $64+8=72$ bits. (5)

• Inequality (2), $k=7$ (1), SECDED +1 (1), total 72 (1).

(b) Non-zero syndrome but overall parity even ⇒ an even number of errors (two bit errors) occurred → double-bit error detected, uncorrectable. Controller flags an uncorrectable error (UE) — logs/raises a machine-check, does not attempt (mis)correction. (4)

(c) Total data bits $=64\text{ GiB}\times 8 = 64\times2^{30}\times8 = 5.4976\times10^{11}$ bits $\approx 5.498\times10^{11}$. Expected single-bit errors/hr $=10^{-14}\times5.498\times10^{11}=5.498\times10^{-3}$ per hour. (≈ $0.0055$ corrected errors/hour, i.e. about one every $182$ hours.) (5)

• Bit count (2), multiply by rate (2), value (1).

[
  {"claim":"Q1a refresh interval = 7.8125 us","code":"interval=Rational(64,1000)/8192; result = abs(float(interval)-7.8125e-6)<1e-12"},
  {"claim":"Q1b refresh overhead = 0.96%","code":"ov=(8192*75e-9)/(64e-3); result = abs(ov*100-0.96)<1e-6"},
  {"claim":"Q2b wordline time = 0.5 ns","code":"t=(200e-15*0.1)/(40e-6); result = abs(t-0.5e-9)<1e-15"},
  {"claim":"Q3c lifetime approx 16.4 years","code":"days=(256*3000)/(40*3.2); yrs=days/365; result = abs(yrs-16.438)<0.01"},
  {"claim":"Q4a DDR4-3200 bandwidth = 25.6 GB/s","code":"bw=1600e6*2*8; result = abs(bw-25.6e9)<1"},
  {"claim":"Q4c total random latency = 30.0 ns","code":"per=1/1600e6; lat=(22+22)*per + 8*(per/2); result = abs(lat*1e9-30.0)<1e-6"},
  {"claim":"Q5a SEC needs 7 check bits for 64 data bits","code":"k=next(k for k in range(1,20) if 2**k>=64+k+1); result = (k==7)"},
  {"claim":"Q5c single-bit corrected errors per hour approx 5.498e-3","code":"bits=64*2**30*8; e=1e-14*bits; result = abs(e-5.498e-3)<1e-4"}
]