Memory Technologies

Q1. (4 marks)

• SRAM: 6 transistors (6T) — 1 mark. Storage element: a cross-coupled pair of inverters (bistable latch) — 1 mark.
• DRAM: 1 transistor + 1 capacitor (1T1C) — 1 mark. Storage element: the capacitor charge — 1 mark. Why: SRAM latches actively hold state; DRAM stores charge passively on a capacitor.

Q2. (4 marks)

• DRAM stores data as charge on a tiny capacitor which leaks away through junction/transistor leakage — 2 marks.
• Refresh periodically reads and rewrites each row to restore full charge (typically every ~64 ms) — 1 mark.
• SRAM's latch is continuously driven by power, so it holds state as long as powered — no leakage of state — 1 mark.
• If not refreshed: charge decays below the sense threshold and data is lost/corrupted — 1 mark (within cap).

Q3. (4 marks — 1 each)

• (a) PROM: programmable once by the user (e.g. blowing fuses); not erasable.
• (b) EPROM: erasable by UV light (whole chip), then reprogrammable electrically.
• (c) EEPROM: electrically erasable and reprogrammable, byte-addressable.
• (d) Mask ROM: contents fixed at manufacture via masking; cannot be changed.

Q4. (6 marks — 1 per correct cell)

Q5. (7 marks)

• (a) DDR transfers data on both rising and falling edges of the clock, giving 2 transfers per clock cycle — 2 marks.
• (b) MT/s $= 1600 \text{ MHz} \times 2 = \mathbf{3200\ MT/s}$ — 2 marks.
• (c) Bandwidth $=$ transfers/s × bytes/transfer $= 3200\times10^6 \times 8\text{ bytes} = 25600\times10^6$ B/s $= \mathbf{25.6\ GB/s}$ — 3 marks. (64-bit path = 8 bytes.)

Q6. (5 marks)

• A floating gate is an electrically isolated gate buried in oxide between control gate and channel — 1 mark.
• Programming: electrons are forced onto the floating gate (via Fowler–Nordheim tunneling / hot-electron injection) — 1 mark.
• Trapped negative charge raises the threshold voltage $V_{th}$ of the transistor — 1 mark.
• Reading applies a fixed control-gate voltage; whether the cell conducts depends on stored charge (high/low $V_{th}$ ⇒ programmed "0"/erased "1") — 1 mark.
• Charge is retained without power (non-volatile); erase removes electrons — 1 mark.

Q7. (5 marks)

• MLC = 2 bits/cell (4 levels) — 1 mark.
• TLC = 3 bits/cell (8 levels) — 1 mark.
• QLC = 4 bits/cell (16 levels) — 1 mark.
• Trade-off increasing with bits/cell (any one, 2 marks): lower endurance / reduced reliability / smaller noise margin / slower writes as more voltage levels must be distinguished.

Q8. (4 marks)

• Flash blocks tolerate a limited number of program/erase (P/E) cycles before wearing out — 2 marks.
• Wear leveling distributes writes evenly across all blocks so no single block is repeatedly cycled — 1 mark.
• This extends overall device lifetime and prevents premature failure of hot blocks — 1 mark.

Q9. (6 marks)

• (a) Check bits $= 72 - 64 = \mathbf{8}$ — 1 mark.
• (b) SECDED = corrects any single-bit error and detects (but not corrects) any double-bit error — 2 marks.
• (c) For single-error correction we need $2^k \ge m+k+1$. With $m=64$: try $k=7$: $2^7=128 \ge 64+7+1=72$ ✓ (7 bits already suffice for SEC) — 2 marks. The 8th bit is the extra overall parity that upgrades SEC to SECDED — 1 mark.

Q10. (6 marks — 1 name + 1 mechanism each)

• MRAM: stores bit as magnetic orientation of a tunnel junction (resistance changes with magnetization).
• ReRAM (RRAM): stores bit as resistance state set by forming/rupturing a conductive filament in a dielectric.
• PCM: stores bit via phase change of chalcogenide material between crystalline (low-R) and amorphous (high-R) states.

[
  {"claim":"DDR4 1600MHz bus gives 3200 MT/s","code":"bus=1600; mt=bus*2; result = (mt==3200)"},
  {"claim":"DDR4-3200 x64 peak bandwidth = 25.6 GB/s","code":"mt=3200e6; bytes=8; bw=mt*bytes/1e9; result = (abs(bw-25.6)<1e-6)"},
  {"claim":"72-64 SECDED uses 8 check bits","code":"result = (72-64 == 8)"},
  {"claim":"k=7 satisfies Hamming SEC bound for m=64","code":"m=64; k=7; result = (2**k >= m+k+1)"}
]