Level 1 — RecognitionMemory Technologies

Memory Technologies

⏱ 20 minutes30 marksprintable — key stays hidden on paper

Subject: Hardware Chapter: 4.1 Memory Technologies Difficulty Level: 1 — Recognition Time Limit: 20 minutes Total Marks: 30

Section A — Multiple Choice (1 mark each)

Select the single best answer.

Q1. A standard SRAM cell is built from how many transistors?

(a) 1 (b) 4 (c) 6 (d) 8

Q2. A DRAM 1T1C cell stores one bit using:

(a) two cross-coupled inverters
(b) one transistor and one capacitor
(c) a floating gate transistor
(d) a sense amplifier latch

Q3. DRAM requires periodic refresh primarily because of:

(a) transistor threshold shift
(b) capacitor charge leakage
(c) bit-line precharge failure
(d) row-decoder timing errors

Q4. Which memory retains data WITHOUT power AND can be electrically erased in-circuit?

(a) SRAM (b) DRAM (c) EEPROM (d) mask ROM

Q5. Compared with NOR flash, NAND flash generally offers:

(a) faster random byte read, lower density
(b) higher density and lower cost per bit
(c) true random access for code execution
(d) no need for a controller

Q6. DDR memory transfers data on:

(a) rising clock edge only
(b) falling clock edge only
(c) both rising and falling clock edges
(d) neither edge, using an internal PLL only

Q7. A TLC flash cell stores how many bits per cell?

(a) 1 (b) 2 (c) 3 (d) 4

Q8. A content-addressable memory (CAM) is accessed by supplying:

(a) a memory address, returning data
(b) data, returning a matching address
(c) a row and column strobe
(d) a refresh command

Q9. The SEC-DED Hamming code can:

(a) correct two-bit errors
(b) correct one-bit and detect two-bit errors
(c) only detect single-bit errors
(d) correct any number of errors

Q10. Which emerging memory stores bits using magnetic tunnel junction resistance?

(a) PCM (b) ReRAM (c) MRAM (d) SRAM

Section B — Matching (1 mark each, 6 marks)

Q11–Q16. Match each term (left) to its best description (right). Write the letter.

#	Term
Q11	Floating gate transistor
Q12	Sense amplifier
Q13	Wear leveling
Q14	PROM
Q15	Memory bandwidth
Q16	Row address strobe (RAS)

Letter	Description
A	Distributes program/erase cycles evenly across flash blocks
B	Detects and amplifies the small voltage on a bit-line
C	Charge trapped on it shifts the transistor threshold voltage
D	Selects a row of the memory array
E	One-time programmable via fuse/antifuse
F	Data transferred per unit time (e.g., GB/s)

Section C — True/False WITH Justification (2 marks each: 1 verdict + 1 reason)

Q17. SRAM is denser (more bits per unit area) than DRAM. True/False — justify.

Q18. Increasing bits-per-cell from SLC to QLC improves endurance (P/E cycles) of a flash device. True/False — justify.

Q19. For a DDR4 module labelled DDR4-3200, the peak transfer rate is 3200 MT/s on a 64-bit bus giving 25.6 GB/s. True/False — justify with a calculation.

Q20. A single parity bit added to a data word can correct any single-bit error. True/False — justify.

End of paper.

Answer keyMark scheme & solutions

Section A (10 marks)

Q1 — (c) 6. The classic SRAM cell uses two cross-coupled inverters (4 transistors) plus 2 access transistors = 6T. (1)

Q2 — (b) one transistor and one capacitor. 1T1C = the defining DRAM structure; the capacitor holds charge, the transistor gates access. (1)

Q3 — (b) capacitor charge leakage. The storage capacitor leaks through the access transistor and substrate, so charge must be periodically restored. (1)

Q4 — (c) EEPROM. Non-volatile and electrically erasable in-circuit (byte-level). SRAM/DRAM are volatile; mask ROM cannot be rewritten. (1)

Q5 — (b) higher density and lower cost per bit. NAND's series string layout gives smaller cell area; NOR gives fast random read for code (execute-in-place). (1)

Q6 — (c) both rising and falling clock edges. "Double Data Rate" doubles throughput vs SDR by using both edges. (1)

Q7 — (c) 3. TLC = Triple-Level Cell = 3 bits ( $2^3=8$ levels). (1)

Q8 — (b) data, returning a matching address. CAM performs parallel search: input = search data, output = match location. (1)

Q9 — (b) correct one-bit and detect two-bit errors. SEC-DED = Single-Error-Correct, Double-Error-Detect. (1)

Q10 — (c) MRAM. Magnetoresistive RAM uses magnetic tunnel junction (MTJ) resistance states. PCM uses phase change; ReRAM uses filament resistance. (1)

Q	Answer	Reason
Q11	C	Trapped charge on floating gate shifts $V_{th}$ .
Q12	B	Amplifies tiny bit-line differential during read.
Q13	A	Spreads P/E cycles to extend flash life.
Q14	E	One-time programmable (fuse/antifuse).
Q15	F	Data throughput per unit time.
Q16	D	Strobe that latches/selects the row.

Section C (8 marks)

Q17 — FALSE. (verdict 1) DRAM (1T1C) is far denser than SRAM (6T); SRAM's 6 transistors make each cell larger. SRAM is faster, not denser. (reason 1)

Q18 — FALSE. (verdict 1) More bits/cell requires finer voltage-level distinction, which is more sensitive to charge disturbance and wear, so endurance decreases (SLC ≫ MLC ≫ TLC ≫ QLC). (reason 1)

Q19 — TRUE. (verdict 1) Calculation: $3200 \text{ MT/s} \times 8 \text{ bytes (64 bits)} = 25600 \text{ MB/s} = 25.6 \text{ GB/s}$ . (reason 1)

Q20 — FALSE. (verdict 1) A single parity bit can only detect a single-bit error (odd number of flips); it gives no position information, so it cannot correct. Correction requires multiple check bits (e.g., Hamming). (reason 1)

[
  {"claim":"TLC stores 3 bits = 8 levels","code":"bits=3; result = (2**bits==8)"},
  {"claim":"DDR4-3200 on 64-bit bus = 25.6 GB/s","code":"MT=3200; bytes=64/8; GBps=MT*bytes/1000; result = (GBps==25.6)"},
  {"claim":"SRAM classic cell uses 6 transistors","code":"inverter_T=4; access_T=2; result = (inverter_T+access_T==6)"},
  {"claim":"QLC = 4 bits = 16 distinguishable levels","code":"result = (2**4==16)"}
]

Section A — Multiple Choice (1 mark each)

Section B — Matching (1 mark each, 6 marks)

Section C — True/False WITH Justification (2 marks each: 1 verdict + 1 reason)

Section A (10 marks)

Section B (6 marks)

Section C (8 marks)