SRAM read - write operations — Hinglish notes

4.1.2 · Hardware › Memory Technologies

80/20 core: Ek SRAM cell do cross-coupled inverters (ek latch) plus do access transistors hote hain. Reading mein wo choti si voltage sense ki jaati hai jo stored bit bit-lines pe daalta hai; writing mein bit-lines ko itna force kiya jaata hai ki latch flip ho jaaye. Neeche jo bhi hai wo bas yeh hai — "har transistor kitna strong hona chahiye taaki read se data destroy na ho aur write actually succeed kare."

The 6T Cell — YEH HAI KYA

Read Operation — KAISE KAAM KARTA HAI

Steps (maano cell Q=0, Q̄=1 hold kar raha hai):

Pre-charge: $B L = \overline{B L} = V_{D D}$ drive karo, phir float karo.
WL assert karo: M5, M6 on ho jaate hain, $Q \to B L$ aur $\overline{Q} \to \overline{B L}$ connect ho jaate hain.
Node $Q = 0$ , $B L$ ko neeche pull karta hai access transistor M5 + pull-down M1 ke through. Node $\overline{Q} = 1$ , $\overline{B L}$ ko high rakhta hai.
Ek chota $Δ V = V_{\overline{B L}} - V_{B L}$ develop hota hai. Sense amp use latch karta hai.

High pre-charge kyun? — Kyunki neeche pull karna easy hai (NMOS strong hota hai); hume sirf cell ko current sink karna chahiye, source nahi.

Read stability — yeh constraint deadly hai

Read ke dauran, $Q = 0$ M5 ke through $B L$ se connected hai jo $V_{D D}$ ke paas hoti hai. Current node Q mein jaati hai, uski voltage $V_{Q} > 0$ tak badh jaati hai. Agar $V_{Q}$ doosre inverter ke switching threshold se upar chala jaaye, toh cell flip ho jaata hai → data destroy ho jaata hai (read upset).

Write Operation — KAISE KAAM KARTA HAI

Steps (cell Q=1 hold kar raha hai, hum 0 write karna chahte hain):

$B L = 0$ , $\overline{B L} = V_{D D}$ drive karo.
WL assert karo → M5, M6 on.
$B L = 0$ node $Q$ ko M5 ke through neeche pull karta hai, cell ke PMOS pull-up M2 se ladte hue. Flip karne ke liye, M5 ko jeetna hoga: $V_{Q}$ trip point se neeche girna chahiye taaki doosra inverter $\overline{Q}$ ko high flip kare, jo phir $Q = 0$ ko reinforce kare (regenerative).

Worked Examples

Common Mistakes

Feynman

Recall Ek 12-saal ke bachhe ko samjhao

Imagine karo do bacche ek see-saw pe hain jo agree karte hain: "tu upar, main neeche." Woh locked position ek 1 ya 0 yaad rakhti hai. Read ke liye, hum dheere se har side ko touch karte hain aur feel karte hain kaun sa upar hai — lekin zyada hard touch karo aur unhe knock over kar doge (isliye neeche wale bacche ko sturdy hona chahiye). Write ke liye, hum deliberately ek side ko itna hard shove karte hain jab tak wo seats exchange na kar lein. Toh reading = gentle feel, writing = firm shove; transistor sizes decide karte hain kitna gentle ya firm.

Flashcards

Ek standard SRAM cell mein kitne transistors hote hain aur wo kya hain?

6 — 4 do cross-coupled inverters (latch) banate hain, 2 access/pass transistors hain jo word-line se gated hain.

SRAM read non-destructive kyun hoti hai (DRAM ke unlike)?

Cross-coupled latch actively powered hai aur apni state restore karta hai; yeh decaying charge ki tarah store nahi hoti, isliye refresh/rewrite ki zaroorat nahi (agar cell ratio > 1 ho).

Read se pehle bit-lines ke saath kya kiya jaata hai?

BL aur BL̄ dono ko VDD tak pre-charge kiya jaata hai, phir floating chhod diya jaata hai, taaki cell ek ko neeche pull kar sake.

Cell ratio (CR) define karo aur uski required range batao.

CR = (W/L)pull-down / (W/L)access, > 1 hona chahiye (≈1.2–2) taaki read ke dauran node voltage low rahe → read stability.

Pull-up ratio (PR) define karo aur uski constraint batao.

PR = (W/L)pull-up / (W/L)access; write succeed karne ke liye < 1 hona chahiye (pull-up access se weaker). Equivalently (W/L)access/(W/L)pull-up ≳ 1.2–1.5.

Read upset kya hota hai?

Read ke dauran, access transistor '0' storage node ki voltage badhata hai; agar yeh inverter trip point se zyada ho jaaye toh latch flip ho jaata hai aur stored bit destroy ho jaati hai.

Write ke dauran dono bit-lines kyun drive karte hain?

Ek node ko low aur doosre ko high force karne ke liye, regenerative cross-coupling ko new state reliably flip karne aur hold karne dene ke liye.

Cell Q=1 store karta hai: read pe kaun sa bit-line droops?

BL̄ (Q̄=0 se connected) droops; BL high rehta hai.

Kaun sa fundamental trade-off access transistor ko constrain karta hai?

Yeh read pe cell disturb karne ke liye itna weak hona chahiye (CR>1) lekin write pe use flip karne ke liye itna strong — yeh ek competing sizing requirement hai.

Connections

DRAM read-write operations — destructive read + refresh vs SRAM ke static latch.
Sense amplifiers — bit-lines pe chota $Δ V$ amplify karta hai.
CMOS inverter — building block; uska trip point stability set karta hai.
Static Noise Margin (SNM) — read/hold stability quantify karta hai (butterfly curve).
Cache memory — jahan 6T SRAM use hota hai (L1/L2).
MOSFET sizing (W/L) — CR aur PR ka origin.