Memory Technologies

Question 1 [10]

(a) [4] The 6T cell: two cross-coupled CMOS inverters storing complementary values at nodes $Q$ and $\overline{Q}$.

• 2× pull-up PMOS (M1, M2) — 1 mark
• 2× pull-down NMOS (M3, M4) forming the two inverters — 1 mark
• 2× NMOS access/pass transistors (M5, M6) connecting $Q,\overline{Q}$ to bitlines $BL, \overline{BL}$ — 1 mark
• Wordline (WL) gates M5/M6; storage is bistable/latching — 1 mark

(b) [4] Read: precharge $BL,\overline{BL}$ high, assert WL. The node holding '0' pulls its bitline down slightly through access + pull-down; sense amp detects the differential (2). If the access transistor is too strong relative to the pull-down NMOS, the '0' node gets pulled up above the switching threshold and can flip the cell — read upset. So we enforce a cell ratio (pull-down width > access width) to keep the read-disturb node voltage below the inverter trip point (2).

(c) [2] Write: driver forces one bitline low; the access transistor must overpower the pull-up PMOS to drag the '1' node below the trip point and flip the latch. This is the pull-up ratio condition; access must be strong enough vs PMOS (opposite requirement to read → careful sizing trade-off).

Question 2 [12]

(a) [4] Constant-current discharge: $\Delta V = V_{DD}-V_{min} = 1.2-0.6 = 0.6\text{ V}$. $Q=CV \Rightarrow \Delta Q = C\,\Delta V$; $t_{ret}=\Delta Q/I = C\,\Delta V/I_{leak}$. $t_{ret} = \dfrac{25\times10^{-15}\times0.6}{1\times10^{-15}} = 15\text{ s}$. (4)

(b) [5]

• Rows $=2^{13}=8192$ (1)
• Total refresh time $= 8192 \times 50\text{ ns} = 409600\text{ ns} = 409.6\ \mu s$ (2)
• Overhead $= \dfrac{409.6\ \mu s}{15\text{ s}} = 2.73\times10^{-5} \approx 0.0027\%$ (2)

(c) [3] Smaller $C$ stores less charge → same leakage empties it faster → shorter $t_{ret}$ → more frequent refresh, wasting bandwidth/power (2). Mitigation: temperature-compensated / per-row (retention-aware) refresh, partial-array self-refresh, or finer-grained refresh scheduling (1).

Question 3 [10]

(a) [4] Bandwidth $= \text{bus width (bytes)} \times \text{transfers/s}$. DDR → 2 transfers per clock. Transfers $= 2\times1600\text{ MHz} = 3200\text{ MT/s}$. $BW = 8\text{ bytes} \times 3200\times10^{6} = 25.6\times10^{9}\text{ B/s} = 25.6\text{ GB/s}$. (4)

(b) [4] "DDR5-6400" → 6400 MT/s per pin (data rate). Base internal/IO clock discussion aside, per-pin = 6.4 Gbit/s (2). Module BW $= 8\text{ bytes} \times 6400\times10^{6} = 51.2\text{ GB/s}$. (2)

(c) [2] Bandwidth = throughput (data/sec); latency = time to first data return of a random access. Latency is dominated by fixed array access/row-activation delays (tRCD, tCAS in ns) that scale poorly, while data rate grows via wider prefetch and faster I/O — so latency in ns stays roughly flat.

Question 4 [12]

(a) [4] A floating gate sits between control gate and channel, fully insulated. Program: high gate voltage → electrons tunnel (Fowler-Nordheim) / hot-electron inject onto the floating gate, raising $V_{th}$ (2). Erase: reverse field removes electrons (tunneling to substrate/source), lowering $V_{th}$ (1). Reading at a fixed gate voltage: high $V_{th}$ = won't conduct (one state), low $V_{th}$ = conducts (other state) (1).

(b) [3] MLC = 2 bits (4 levels), TLC = 3 bits (8 levels), QLC = 4 bits (16 levels) (2). General: $L = 2^{n}$ (1).

(c) [3] TLC = 3 bits/cell × $2^{20}$ cells $= 3\times2^{20}$ bits $= 3145728$ bits $= 393216$ bytes (384 KiB) (2). QLC = 4 bits/cell = $4\times2^{20}=524288$ bytes; extra $= 524288-393216 = 131072$ bytes (128 KiB) (1).

(d) [2] More levels pack $V_{th}$ windows tighter → smaller margins, more sensitive to charge loss/disturb → more program-verify iterations and stronger ECC → higher write/read latency; and tighter windows tolerate less oxide degradation → fewer P/E cycles (lower endurance).

Question 5 [10]

(a) [3] SEC needs $2^{p} \ge d + p + 1$ (must uniquely address $d+p$ bit positions plus the no-error syndrome). Try $p=7$: $2^7=128 \ge 64+7+1=72$ ✓; $p=6$: $64 \ge 71$ ✗. So $p=7$. (3)

(b) [5] Positions 1–7; parity at 1,2,4; data $d_1d_2d_3d_4=1,0,1,1$ at positions 3,5,6,7. Layout: $p_1\,p_2\,d_1\,p_4\,d_2\,d_3\,d_4 = p_1\,p_2\,1\,p_4\,0\,1\,1$.

• $p_1$ covers 1,3,5,7 = $p_1,1,0,1 \Rightarrow$ parity of $\{1,0,1\}=0 \Rightarrow p_1=0$ (even).
• $p_2$ covers 2,3,6,7 = $p_2,1,1,1 \Rightarrow$ parity of $\{1,1,1\}=1 \Rightarrow p_2=1$.
• $p_4$ covers 4,5,6,7 = $p_4,0,1,1 \Rightarrow$ parity of $\{0,1,1\}=0 \Rightarrow p_4=0$. Codeword (pos1..7): $0\,1\,1\,0\,0\,1\,1$. (5)

(c) [2] SEC-DED = Single-Error-Correct, Double-Error-Detect. Costs one extra overall parity bit beyond SEC (here 8 bits for 64 data → the common ECC DIMM 72/64 scheme).

Question 6 [6]

(a) [3] CAM is searched by content, not address: you present a data word and it returns the address(es)/match line where that word is stored in one cycle (parallel compare across all rows) (2). Application: network router TAG/forwarding lookup, TLBs, cache tag matching (1).

(b) [3] Flash cells have limited P/E cycles; concentrating writes on few blocks wears them out early — wear leveling spreads writes evenly (1). Dynamic: only remaps blocks currently being written (free/hot data) (1). Static: also relocates rarely-changing (cold) data so those low-wear blocks join the pool, evening wear across the whole device (1).

[
  {"claim":"DRAM retention time = 15 s","code":"C=25e-15; dV=0.6; I=1e-15; t=C*dV/I; result = abs(t-15)<1e-9"},
  {"claim":"Total refresh time = 409.6 us for 2^13 rows at 50ns","code":"rows=2**13; tot=rows*50e-9; result = abs(tot-409.6e-6)<1e-12"},
  {"claim":"DDR-1600 64-bit BW = 25.6 GB/s","code":"bw=8*2*1600e6; result = abs(bw-25.6e9)<1"},
  {"claim":"DDR5-6400 64-bit BW = 51.2 GB/s","code":"bw=8*6400e6; result = abs(bw-51.2e9)<1"},
  {"claim":"TLC 2^20 cells = 393216 bytes; QLC extra 131072 bytes","code":"tlc=3*(2**20)//8; qlc=4*(2**20)//8; result = (tlc==393216) and (qlc-tlc==131072)"},
  {"claim":"SEC parity bits for 64 data = 7","code":"d=64; p=1;\nwhile 2**p < d+p+1: p+=1\nresult = (p==7)"},
  {"claim":"(7,4) Hamming encode of 1011 = 0110011","code":"d1,d2,d3,d4=1,0,1,1; p1=(d1+d2+d4)%2; p2=(d1+d3+d4)%2; p4=(d2+d3+d4)%2; cw=[p1,p2,d1,p4,d2,d3,d4]; result = cw==[0,1,1,0,0,1,1]"}
]