4.1.3
Ek DRAM bit bas ek tiny bucket of charge hai. Ek capacitor paani (bit) hold karta hai, aur ek transistor wo tap hai jo paani andar ya bahar jane deta hai. Yahi poora idea hai: 1 Transistor + 1 Capacitor = 1T1C . Baki sab kuch (leakage, refresh, sense amps) isliye exist karta hai kyunki bucket choti aur leaky hai.
Itne kam components kyun? Kyunki memory density sabse zaroori cheez hai. Agar har bit mein 6 transistors lagte hain (jaise SRAM mein), toh ek chip mein bahut kam bits fit honge. DRAM speed aur simplicity ki trade-off karke chhote se chhota cell banata hai — ideally 6 F 2 4 F 2 F
Ek 1T1C DRAM cell ek bit ko storage capacitor C s access transistor (ek NMOS pass transistor) ke through access kiya jaata hai.
Wordline (WL) → transistor ka gate. WL on karna = tap kholna.Bitline (BL) → source/drain side; read/write ke dauran charge andar/bahar le jaati hai.Storage node → capacitor ki woh plate jo actually bit hold karti hai.Logic 1 = capacitor charged (near V D D 0 = capacitor discharged (near 0 V D D /2
Capacitor charge store karta hai:
Q = C s ⋅ V ce l l
Yeh kyun? Capacitor ka defining relation hai Q = C V hi hai voltage V ce l l C s V V
BL ko desired voltage par drive karo (V D D 0
WL raise karo → transistor conduct karta hai → C s
WL lower karo → transistor off → charge isolated storage node par trap ho jaata hai.
WL last mein kyun lower karte hain? Jab tap band ho jaata hai, storage node float karta hai, toh charge ke paas jaane ki asaan jagah nahi hoti — ab woh "stored" hai.
Read karna wahan hai jahan physics interesting ho jaati hai. Bitline ki apni badi capacitance C B L C B L ≫ C s
Read karne se pehle, hum bitline ko V D D /2 precharge karte hain. Phir WL raise karte hain aur C s C B L
Aise derive kyun karte hain? Transistor bas do capacitors ko connect karta hai; koi charge create ya destroy nahi hota, isliye charge conservation sab kuch de deta hai. Factor C s + C B L C s kuch tens of millivolts se nudge karta hai — isliye humein ek sense amplifier chahiye jo Δ V
"Destructive" kyun? Charge sharing ke baad, V ce l l V D D /2 kharab ho jaati hai, isliye sense amp ko har read ke baad bit write back karni padti hai.
Capacitor junction leakage aur "off" transistor mein subthreshold current ke through charge leak karta hai. Ek "1" dheere dheere "0" ki taraf decay karta hai. Isliye poori chip ko periodically read-and-rewrite karna padta hai — typically har 64 ms (ya high temperature par 32 ms). Woh periodic top-up hi refresh hai, aur isliye isse D ynamic RAM kaha jaata hai.
Leakage discharge ek RC decay follow karta hai:
V ce l l ( t ) = V D D e − t / ( R l e ak C s )
Exponential kyun? Ek R l e ak C d t d V = − V / R l e ak V ce l l
Example 1 — Signal swing. Maano C s = 20 fF C B L = 200 fF V D D = 1.2 V V ce l l = 1.2 Δ V = 20 + 200 20 ( 1.2 − 0.6 ) = 220 20 × 0.6 ≈ 0.0545 V = 54.5 mV Yeh step kyun? Hum derived swing formula mein values plug in karte hain. V D D /2
Example 2 — Reading a "0". Same caps, V ce l l = 0 Δ V = 220 20 ( 0 − 0.6 ) = − 0.0545 V Negative kyun? Cell precharged bitline ko neeche kheenchta hai, isliye sense amp BL ko V D D /2 V D D /2
Example 3 — Stored charge & refresh margin. C s = 20 fF V D D = 1.2 V Q = C s V = 20 × 1 0 − 15 × 1.2 = 2.4 × 1 0 − 14 C = 24 fC Care kyun karein? Yeh roughly 1.5 × 1 0 5
"DRAM read non-destructive hota hai, jaise ek variable read karna."
Kyun sahi lagta hai: Software aur SRAM mein reading kabhi data change nahi karti. Fix: DRAM read charge-sharing hai, jo cell voltage ko dilute karta hai — bit destroy ho jaata hai aur sense amp ko har access ke baad rewrite karna padta hai.
"Bada C B L
Kyun sahi lagta hai: Zyada capacitance matlab zyada signal lagta hai. Fix: Δ V = C s + C B L C s ( … ) C B L shrink karta hai. Designers bitlines ko chota rakhte hain (segmented arrays) taaki C B L C s
"Refresh isliye chahiye kyunki transistor kharab hai."
Kyun sahi lagta hai: Hum tap ko leaking ke liye blame karte hain. Fix: Ek near-ideal transistor mein bhi junction & subthreshold leakage hoti hai, aur C s deliberately tiny hai. Chota charge + koi bhi leakage = data decay. Refresh ek fundamental consequence hai, koi defect nahi.
"0
Kyun sahi lagta hai: Empty se start karo, reason karna easy hai. Fix: V D D /2 symmetrically — yeh worst-case swing ko aadha kar deta hai aur differential sense amp ko ek reference ke against compare karne deta hai.
Recall Feynman: explain to a 12-year-oldSocho ki har bit ek choti si paani ki cup hai jisme ek tap laga hai. Bhari cup = 1, khaali cup = 0. Cup read karne ke liye, use ek giant tank se connect karte ho; paani ka level thoda hi badalta hai, isliye tumhe ek super-sensitive gauge chahiye (sense amp) jo bataye "kya yeh bhari thi ya khaali thi?". Lekin tank se connect karne par cup spill ho jaati hai, isliye turant refill karna padta hai. Saath hi, cups dheere dheere leak karti hain, isliye har 64 milliseconds mein ek helper saari bhari cups ko top up karne jaata hai. Woh topping-up hi refresh kehlaata hai, aur isliye isse Dynamic RAM kehte hain.
"One Tap, One Cup — Dilute, Sense, Refill, Refresh."
1 T ransistor (Tap) + 1 C apacitor (Cup)
D ilute (charge share) → S ense (amplify) → R efill (write-back) → R efresh (leaky cup).
1T1C DRAM cell ke do components kya hain? Ek access (NMOS) transistor aur ek storage capacitor C s
Transistor gate se kaunsi line connect hoti hai? Wordline (WL).
Read/write ke dauran charge andar/bahar kaunsi line le jaati hai? Bitline (BL).
DRAM read ko "destructive" kyun kaha jaata hai? C s C B L
Bitline par signal-swing formula likhiye. Δ V = C s + C B L C s ( V ce l l − 2 V D D )
Bitline ko V D D /2 Taaki "1" upar swing kare aur "0" neeche symmetrically, differential sense amp ke liye.
Swing formula small Δ V Kyunki C B L ≫ C s
DRAM mein "D" kya stand karta hai aur kyun? Dynamic — capacitor leak karta hai, isliye data ko periodically refresh karna padta hai.
Typical refresh interval? ~64 ms (≈32 ms at high temperature).
SRAM ke 6T ki jagah 1T1C kyun? Bahut zyada density (per bit kam transistors) → per bit sasta.
"1" hold karne wale cell par stored charge? Q = C s V D D
Choti bitline signal ko full logic level par kya amplify karta hai? Sense amplifier.
SRAM 6T cell — fast, non-destructive, low-density counterpart.Sense Amplifiers — zaroorat hai kyunki Δ V DRAM Refresh — capacitor leakage ka direct consequence.Charge Sharing — destructive reads ke peeche ki physics.Bitline and Wordline Architecture — cells arrays mein kaise wired hote hain.Capacitor Q=CV — woh fundamental relation jo bit store karta hai.
because CBL greater than Cs
Destructive read needs rewrite
