DRAM refresh and charge leakage

WHY does DRAM need refresh at all?

WHY does the charge disappear? The capacitor is not perfect. Three leakage paths drain it:

Subthreshold leakage through the "off" access transistor (it's never perfectly off).
Junction leakage at the reverse-biased diode between the storage node and the substrate.
Dielectric leakage through the (very thin) capacitor insulator itself.

Because the cell is "dynamic" (charge decays over time), it contrasts with SRAM, which is "static" — SRAM holds its bit in a cross-coupled latch that actively drives the value and never needs refresh (but costs 6 transistors per bit).

HOW does the charge actually decay? (Derivation from first principles)

Model the leakage as a resistance $R_{leak}$ from the storage node to ground. The capacitor $C$ discharges through it.

Step 1 — Charge conservation. Current leaving the capacitor equals the drop in stored charge: $I = -\frac{dQ}{dt}, \qquad Q = C\,V \;\Rightarrow\; I = -C\frac{dV}{dt}$ Why this step? The only place the charge can go is through the leak, so rate of charge loss = leakage current.

Step 2 — Ohm's law on the leak path. $I = V / R_{leak}$ . Why? The leak behaves (to first order) like a resistor draining the node to $0\,\text{V}$ .

Step 3 — Combine into an ODE. $-C\frac{dV}{dt} = \frac{V}{R_{leak}} \;\Rightarrow\; \frac{dV}{dt} = -\frac{V}{R_{leak}C}$

Step 4 — Solve. Separable, giving exponential decay: $\boxed{V(t) = V_0\, e^{-t/\tau}, \qquad \tau = R_{leak}\,C}$ Why? Any "rate of change $\propto$ current amount" gives an exponential — the same math as RC discharge or radioactive decay.

The refresh rule: you must revisit every cell within one refresh period $t_{REF}$ (the standard is $64\,\text{ms}$ at normal temperature, tightened to $32\,\text{ms}$ when hot). You must choose $t_{REF} < t_{ret}$ of the weakest cell in the entire chip.

Figure — DRAM refresh and charge leakage

HOW is refresh performed?

Distributed vs burst.

Burst refresh: refresh all rows back-to-back, then run normal accesses. Memory is unavailable during the burst.
Distributed refresh: spread refreshes evenly. For $N$ rows in period $t_{REF}$ , issue one REF every $t_{RI} = \frac{t_{REF}}{N} \quad\text{(refresh interval)}.$ Modern DDR uses distributed refresh so no single long stall occurs.

Temperature & why hot DRAM refreshes twice as fast

Leakage currents rise roughly exponentially with temperature (junction/subthreshold currents follow $\propto e^{-E_a/kT}$ -type behavior). Higher $T$ → smaller $R_{leak}$ → smaller $\tau$ → shorter retention. So JEDEC halves the period to $32\,\text{ms}$ above $85^\circ\text{C}$ ("temperature-compensated / auto self-refresh").

Common mistake Steel-manned misconceptions

"Every cell must be refreshed at exactly the same rate because it's a fixed spec." Why it feels right: the datasheet gives one number ( $64$ ms), so it seems uniform. The truth: retention varies wildly cell-to-cell. The spec is set by the weakest cell. Research (RAIDR, retention profiling) exploits the fact that most cells could go far longer, saving power by refreshing strong cells less.

"Reading data destroys it, so reads are bad for DRAM." Why it feels right: DRAM reads are destructive (the row dumps its charge). The fix: the sense amps immediately restore the row, so a read is also a refresh. No data is lost.

"Refresh copies data to a buffer and back." Why it feels right: "refresh" sounds like moving/rewriting. The fix: nothing moves anywhere — activating the row and letting the sense amp re-drive the bitline regenerates the full-voltage level in place.

Recall Explain it to a 12-year-old (click to reveal)

Imagine a giant wall of tiny cups. A full cup means "1", an empty cup means "0". But every cup has a slow leak. If you leave them alone, all the full cups slowly empty and the computer forgets everything! So a little robot walks along the wall, and every few thousandths of a second it checks a row of cups and tops up the full ones back to full. That topping-up is called refresh. Cups leak faster when it's hot, so the robot walks twice as fast on a hot day. This is why turning off the power erases DRAM — the robot stops, the cups drain, and the memory forgets.

Flashcards

What is the physical structure of one DRAM cell?

One transistor + one capacitor (1T1C); the bit is charge stored on the capacitor.

Why is DRAM called "dynamic"?

Because stored charge leaks and decays over time, so it must be periodically refreshed (vs static SRAM which holds its bit in a latch).

Name the three main leakage paths in a DRAM cell.

Subthreshold leakage through the access transistor, junction (reverse-bias diode) leakage, and dielectric leakage through the capacitor insulator.

Derive the voltage decay law of a leaky DRAM cell.

I=-C\,dV/dt

and

I=V/R

give

dV/dt=-V/(RC)

, so

V(t)=V_0 e^{-t/\tau}

with

\tau=RC

What is retention time in terms of τ if threshold = V0/2?

t_{ret}=\tau\ln(V_0/V_{th})=\tau\ln 2\approx 0.693\,\tau

What is the standard DRAM refresh period at normal temperature?

64 ms (halved to 32 ms above ~85°C).

How is the refresh interval computed for N rows?

t_{RI}=t_{REF}/N

; e.g. 64ms / 8192 rows ≈ 7.8 µs per REF.

Difference between burst and distributed refresh?

Burst refreshes all rows consecutively (long stall); distributed spreads them evenly (one every t_REF/N) to avoid a single big pause.

Why does reading a DRAM row also refresh it?

Activating a row is destructive but the sense amplifiers immediately restore the full-voltage level in place.

Why does hot DRAM need faster refresh?

Leakage currents rise ~exponentially with temperature, shrinking τ and retention time, so the period must be shortened.

What sets the required refresh period across the whole chip?

The weakest (fastest-leaking) cell — the whole array is refreshed at the rate that keeps that cell above threshold.

Formula for refresh time overhead?

t_RFC / t_RFI (busy time per refresh ÷ interval between refreshes).

Connections

SRAM vs DRAM — why SRAM needs no refresh (latch vs capacitor)
Sense Amplifiers — the circuit that detects and restores the row
RC time constant — same exponential-decay math
DDR SDRAM timing parameters — $t_{RFC}$ , $t_{REFI}$ , $t_{RAS}$
Capacitance Q=CV — foundation for stored-charge reasoning
Low-power DRAM self-refresh — retention-aware and temperature-compensated refresh

Concept Map

Hinglish (regional understanding)

Intuition Hinglish mein samjho

Dekho, DRAM ka har ek bit sirf ek chhoti si capacitor pe stored charge hota hai — charge hai to "1", nahi hai to "0". Problem yeh hai ki yeh capacitor perfect nahi hota, uska charge dheere-dheere leak ho jaata hai (transistor se, junction se, aur dielectric se). Matlab agar kuch na karo to memory apne aap sab bhool jaayegi kuch milliseconds mein. Isiliye DRAM ko "dynamic" bolte hain — data ko zinda rakhne ke liye baar-baar refresh karna padta hai.

Physics simple hai: charge $Q=CV$ , aur leakage current $I = V/R$ . Isse equation banti hai $dV/dt = -V/(RC)$ , jiska solution hai $V(t)=V_0 e^{-t/\tau}$ jahan $\tau = RC$ . Yaani voltage exponentially girta hai. Jab tak voltage sense amplifier ke threshold (aam taur pe $V_0/2$ ) se upar hai, tab tak bit sahi padha ja sakta hai. Iske niche gir gaya to bit corrupt. Isiliye har cell ko us threshold tak pahunchne se pehle top-up karna zaroori hai — yahi refresh hai.

Practically, DRAM ek pura row ek saath refresh karta hai. Standard period 64 ms hai (garmi mein $85^\circ$ C ke upar 32 ms, kyunki heat se leakage exponentially badhta hai). Agar bank mein 8192 rows hain to har $64\text{ms}/8192 \approx 7.8\,\mu s$ mein ek REF command aati hai — isko distributed refresh kehte hain, taaki ek lamba stall na ho. Ek mazedaar baat: DRAM ka read destructive hota hai, par sense amp turant value wapas likh deta hai, isliye read khud bhi refresh kar deta hai.

Yeh important kyun hai? Kyunki refresh se performance aur power dono affect hote hain — bade chips mein overhead 5% se 20% tak ja sakta hai. Aur exam/interview mein yahi concept baar-baar aata hai: "DRAM refresh kyun chahiye?" — jawab: capacitor leaks, charge decays exponentially, refresh regenerates it before crossing threshold. Bas yeh yaad rakho.

WHY does DRAM need refresh at all?

HOW does the charge actually decay? (Derivation from first principles)

HOW is refresh performed?

Temperature & why hot DRAM refreshes twice as fast

Flashcards

Connections

Concept Map

Hinglish (regional understanding)

Go deeper — visual, from zero

Test yourself — Memory Technologies

Connections