DRAM refresh and charge leakage — Hinglish notes

4.1.4 · Hardware › Memory Technologies

DRAM ko refresh ki zaroorat HAI KYU?

Charge kyu gayab hota hai? Capacitor perfect nahi hota. Teen leakage paths use drain karte hain:

Subthreshold leakage "off" access transistor se hoke (woh kabhi perfectly off nahi hota).
Junction leakage storage node aur substrate ke beech reverse-biased diode par.
Dielectric leakage capacitor ke (bahut patle) insulator se hoke.

Kyunki cell "dynamic" hai (charge time ke saath decay hota hai), yeh SRAM se contrast karta hai, jo "static" hai — SRAM apna bit ek cross-coupled latch mein hold karta hai jo value ko actively drive karta hai aur kabhi refresh ki zaroorat nahi padti (lekin per bit 6 transistors lagte hain).

Charge actually kaise decay karta hai? (First principles se derivation)

Leakage ko ek resistance $R_{l e ak}$ ke roop mein model karo jo storage node se ground tak jaata hai. Capacitor $C$ iske through discharge hota hai.

Step 1 — Charge conservation. Capacitor se nikalta current = stored charge mein kami ki dar: $I = - \frac{d Q}{d t}, Q = C V \Rightarrow I = - C \frac{d V}{d t}$ Yeh step kyu? Charge sirf leak ke through ja sakta hai, isliye charge loss ki dar = leakage current.

Step 2 — Leak path par Ohm's law. $I = V / R_{l e ak}$ . Kyu? Leak (first order mein) ek resistor jaisa behave karta hai jo node ko $0 V$ par drain karta hai.

Step 3 — ODE mein combine karo. $- C \frac{d V}{d t} = \frac{V}{R _{l e ak}} \Rightarrow \frac{d V}{d t} = - \frac{V}{R _{l e ak} C}$

Step 4 — Solve karo. Separable hai, exponential decay deta hai: $V (t) = V_{0} e^{- t / τ}, τ = R_{l e ak} C$ Kyu? Koi bhi "rate of change $\propto$ current amount" exponential deta hai — same math RC discharge ya radioactive decay jaisi.

Refresh ka rule: tumhe har cell ko ek refresh period $t_{R E F}$ ke andar revisit karna hi hoga ( $64 ms$ normal temperature par standard hai, hot hone par $32 ms$ ho jaata hai). Tumhe $t_{R E F} < t_{r e t}$ weakest cell ka poore chip mein choose karna hoga.

Figure — DRAM refresh and charge leakage

Refresh KAISE perform hota hai?

Distributed vs burst.

Burst refresh: saari rows ko back-to-back refresh karo, phir normal access chalaao. Burst ke dauran memory unavailable hoti hai.
Distributed refresh: refreshes ko evenly spread karo. $N$ rows ke liye period $t_{R E F}$ mein, har ek REF dete hain $t_{R I} = \frac{t _{R E F}}{N} (refresh interval) .$ Modern DDR distributed refresh use karta hai taaki koi ek lamba stall na aaye.

Temperature aur kyu hot DRAM double speed se refresh karta hai

Leakage currents temperature ke saath roughly exponentially badhti hain (junction/subthreshold currents $\propto e^{- E_{a} / k T}$ -type behavior follow karte hain). Zyada $T$ → chhota $R_{l e ak}$ → chhota $τ$ → shorter retention. Isliye JEDEC $8 5^{\circ} C$ se upar period ko $32 ms$ kar deta hai ("temperature-compensated / auto self-refresh").

Common mistake Steel-manned misconceptions

"Har cell ko exactly usi rate par refresh karna padta hai kyunki yeh ek fixed spec hai." Yeh sahi kyun lagta hai: datasheet ek number deta hai ( $64$ ms), toh lagta hai yeh uniform hai. Sach: retention cell-to-cell bahut vary karta hai. Spec weakest cell ke hisaab se set hoti hai. Research (RAIDR, retention profiling) is baat ka fayda uthata hai ki zyatar cells kaafi zyada der tak chal sakti hain, strong cells ko kam refresh karke power bachata hai.

"Data padhne se woh destroy hota hai, toh reads DRAM ke liye bure hain." Yeh sahi kyun lagta hai: DRAM reads are destructive (row apna charge dump kar deti hai). Fix: sense amps turant row restore karte hain, toh ek read ek refresh bhi hai. Koi data nahi jaata.

"Refresh data ko ek buffer mein copy karta hai aur wapas laata hai." Yeh sahi kyun lagta hai: "refresh" sunne mein moving/rewriting jaisa lagta hai. Fix: kuch kahin nahi jaata — row ko activate karna aur sense amp ko bitline re-drive karne dena full-voltage level ko wahin regenerate karta hai.

Recall Ise ek 12-saal ke bacche ko samjhao (click to reveal)

Ek aisi badi diwar ki kalpana karo jisme chhoti chhoti cups hain. Bhari cup matlab "1", khaali cup matlab "0". Lekin har cup mein dheeri leak hai. Agar unhe akela chod do, toh saari bhari cups dheere dheere khaali ho jaayengi aur computer sab bhool jaayega! Toh ek chhota robot diwar ke saath saath chalta hai, aur har kuch hajaarvein seconds mein woh cups ki ek row check karta hai aur bhari huyi cups ko wapas bhar deta hai. Usi topping-up ko refresh kehte hain. Cups garam hone par zyada tezi se leak karti hain, toh robot garam din mein double speed se chalta hai. Isliye DRAM se power band karne par sab erase ho jaata hai — robot ruk jaata hai, cups drain ho jaati hain, aur memory bhool jaati hai.

Flashcards

Ek DRAM cell ka physical structure kya hai?

Ek transistor + ek capacitor (1T1C); bit capacitor par stored charge hai.

DRAM ko "dynamic" kyu kehte hain?

Kyunki stored charge leak hota hai aur decay karta hai, isliye ise periodically refresh karna padta hai (vs static SRAM jo apna bit ek latch mein hold karta hai).

DRAM cell mein teen main leakage paths kaunse hain?

Access transistor se subthreshold leakage, junction (reverse-bias diode) leakage, aur capacitor insulator se dielectric leakage.

Ek leaky DRAM cell ka voltage decay law derive karo.

I = - C d V / d t

aur

I = V / R

d V / d t = - V / (R C)

milta hai, toh

V (t) = V_{0} e^{- t / τ}

jahan

τ = R C

Threshold = V0/2 ho toh τ ke terms mein retention time kya hai?

t_{r e t} = τ ln (V_{0} / V_{t h}) = τ ln 2 \approx 0.693 τ

Normal temperature par standard DRAM refresh period kya hai?

64 ms (~85°C se upar 32 ms ho jaata hai).

N rows ke liye refresh interval kaise compute hota hai?

t_{R I} = t_{R E F} / N

; e.g. 64ms / 8192 rows ≈ 7.8 µs per REF.

Burst aur distributed refresh mein kya fark hai?

Burst saari rows ko consecutively refresh karta hai (lamba stall); distributed unhe evenly spread karta hai (har t_REF/N par ek) taaki ek bada pause na aaye.

DRAM row padhne se usse refresh kyu ho jaata hai?

Row activate karna destructive hota hai lekin sense amplifiers turant full-voltage level in-place restore kar dete hain.

Hot DRAM ko zyada tez refresh ki zaroorat kyu hoti hai?

Leakage currents temperature ke saath ~exponentially badhti hain, τ aur retention time chhota ho jaata hai, toh period chhota karna padta hai.

Poore chip ka required refresh period kya set karta hai?

Weakest (sabse tezi se leaking) cell — poori array us rate par refresh hoti hai jo us cell ko threshold se upar rakhe.

Refresh time overhead ka formula kya hai?

t_RFC / t_RFI (har refresh par busy time ÷ refreshes ke beech interval).

Connections

SRAM vs DRAM — kyu SRAM ko refresh nahi chahiye (latch vs capacitor)
Sense Amplifiers — woh circuit jo row detect aur restore karta hai
RC time constant — same exponential-decay math
DDR SDRAM timing parameters — $t_{R F C}$ , $t_{R E F I}$ , $t_{R A S}$
Capacitance Q=CV — stored-charge reasoning ka foundation
Low-power DRAM self-refresh — retention-aware aur temperature-compensated refresh