DRAM refresh and charge leakage: Exercises — Hardware deep dive

Before we start, one shared picture of the quantities we will keep reusing. Every symbol below is earned here so you never meet it cold later.

Definition The cast of symbols (read once, refer back forever)

$C$ — capacitance of the storage cap, "how much charge per volt" (unit: farad, $F$ ). We use $fF = 1 0^{- 15} F$ .
$V$ — voltage on the storage node, "how full the bucket is." $V_{0}$ is the fresh full-charge voltage.
$Q = C V$ — charge stored (unit: coulomb). See Capacitance Q=CV.
$I_{l e ak}$ — the tiny leakage current draining the node (unit: ampere; we use $fA = 1 0^{- 15} A$ ).
$R_{l e ak}$ — an effective resistance modelling that leak.
$τ = R_{l e ak} C$ — the time constant, "the natural timescale of the decay." See RC time constant.
$V_{t h}$ — the sense threshold, the "half-full line" the sense amp uses to call 1 vs 0.
$t_{r e t}$ — retention time, how long a cell stays readable.
$t_{R E F}$ — the refresh period (spec: $64 ms$ , or $32 ms$ when hot).
$N$ — number of rows in a bank; $t_{R I} = t_{R E F} / N$ — the refresh interval between REF commands.
$t_{R F C}$ — how long one REF command keeps the bank busy.

Level 1 — Recognition

Problem L1.1

Which of these needs periodic refresh, and why: (a) a DRAM cell, (b) an SRAM cell?

Recall Solution

(a) DRAM needs refresh. Its bit is charge $Q = C V$ on a capacitor that leaks — the "dynamic" in Dynamic RAM. Left alone, $V$ decays and a stored 1 eventually looks like a 0. (b) SRAM does not. It holds its bit in a cross-coupled latch that actively drives the value from the supply rails. Nothing decays as long as power is on. See SRAM vs DRAM. Recognition test: "does the storage element passively hold charge, or actively drive?" Passive → refresh; active → none.

Problem L1.2

A cell decays as $V (t) = V_{0} e^{- t / τ}$ . Without computing, is the voltage after one $τ$ closer to $37%$ or $50%$ of $V_{0}$ ?

Recall Solution

At $t = τ$ : $V = V_{0} e^{- 1} = 0.3679 V_{0} \approx 37%$ . So closer to $37%$ . The number $e^{- 1} \approx 0.37$ is the signature of "one time constant has passed" — memorise it. See RC time constant.

Level 2 — Application

Problem L2.1

A bank has $N = 16384$ rows and $t_{R E F} = 64 ms$ . Using distributed refresh, how often must a REF command fire?

Recall Solution

WHAT: we spread $16384$ refreshes evenly across $64 ms$ . WHY: distributed refresh avoids one long stall; each REF handles one row, so the gap between them is $t_{R I} = \frac{t _{R E F}}{N} = \frac{64 \times 1 0 ^{- 3} s}{16384} = 3.906 \times 1 0^{- 6} s \approx 3.9 μ s .$ Notice: double the rows → half the interval compared to the parent's 8192-row example ( $7.8 μ s$ ). More rows in the same $64 ms$ means firing REFs twice as often. See DDR SDRAM timing parameters.

Problem L2.2

A cell has $C = 30 fF$ , constant leakage $I_{l e ak} = 2 fA$ , $V_{0} = 1.0 V$ , $V_{t h} = 0.5 V$ . Using the constant-current (linear) model, how long until it crosses threshold?

Recall Solution

WHAT: find the time to remove the charge $Δ Q = C Δ V$ at a steady current. WHY constant current, not exponential? For a first estimate we assume the leak drains a fixed $I_{l e ak}$ regardless of $V$ . Then charge leaves at a constant rate, so $Δ t = Δ Q / I_{l e ak}$ . $Δ V = V_{0} - V_{t h} = 0.5 V, Δ t = \frac{C Δ V}{I _{l e ak}} = \frac{30 \times 1 0 ^{- 15} \times 0.5}{2 \times 1 0 ^{- 15}} = 7.5 s .$ A healthy cell survives seconds — yet the spec is $64 ms$ . That gap exists because the weakest cells leak far worse (next levels).

Problem L2.3

Same $C = 30 fF$ cell, but now model the leak as a resistor $R_{l e ak} = 2 \times 1 0^{12} Ω$ (2 TΩ). Find $τ$ and the retention time with $V_{t h} = V_{0} /2$ .

Recall Solution

WHAT: compute the RC time constant, then the exponential retention. $τ = R_{l e ak} C = (2 \times 1 0^{12}) (30 \times 1 0^{- 15}) = 0.06 s = 60 ms .$ With $V_{t h} = V_{0} /2$ , the exponential crosses threshold when $e^{- t / τ} = 1/2$ : $t_{r e t} = τ ln 2 = 0.06 \times 0.6931 = 0.0416 s \approx 41.6 ms .$ WHY $ln 2$ : solving $V_{0} e^{- t / τ} = V_{0} /2$ gives $t / τ = ln 2$ . This $41.6 ms$ is below $64 ms$ — this modelled cell would fail! It shows why weak cells force the spec.

Level 3 — Analysis

Problem L3.1

Two decay models for the same cell ( $C = 30 fF$ , $V_{0} = 1 V$ , $V_{t h} = 0.5 V$ ): a linear drain giving $t_{r e t, lin}$ , and an exponential with $τ = 60 ms$ giving $t_{r e t, exp} = 41.6 ms$ . If the initial leakage current is the same, which model predicts a longer retention, and why (physically)?

Recall Solution

Match the initial current. At $t = 0$ the exponential leak current is $I_{0} = V_{0} / R_{l e ak} = 1/ (2 \times 1 0^{12}) = 5 \times 1 0^{- 13} A = 0.5 pA$ . Feed that same current into the linear model: $t_{r e t, lin} = \frac{C Δ V}{I _{0}} = \frac{30 \times 1 0 ^{- 15} \times 0.5}{5 \times 1 0 ^{- 13}} = 0.03 s = 30 ms .$ So the exponential model retains longer ( $41.6 ms > 30 ms$ ). WHY physically: in the resistor (exponential) model, as $V$ falls the current $V / R$ also falls — the drain slows down as the bucket empties. The linear model keeps draining at the full initial rate the whole way. A self-slowing leak buys extra time. This is the geometric meaning of the curve bending flatter (see figure s02).

Problem L3.2

The parent gives refresh overhead $= t_{R F C} / t_{R F I}$ . A chip has $t_{R F C} = 350 ns$ and $N = 8192$ rows at $t_{R E F} = 64 ms$ . The next generation doubles rows to $16384$ (same $64 ms$ ) and $t_{R F C}$ grows to $550 ns$ . Compute both overheads and the relative increase.

Recall Solution

Gen 1: $t_{R F I} = 64 ms /8192 = 7.8125 μ s$ . Overhead $= 350/7812.5 = 0.0448 = 4.48%$ . Gen 2: $t_{R F I} = 64 ms /16384 = 3.90625 μ s$ . Overhead $= 550/3906.25 = 0.1408 = 14.08%$ . WHY it explodes: overhead $= t_{R F C} \cdot N / t_{R E F}$ . Doubling $N$ and raising $t_{R F C}$ both multiply upward while $t_{R E F}$ stays pinned at $64 ms$ . Relative increase $= 14.08/4.48 = 3.14 \times$ — more than triple the lost time. This is the real "refresh wall" as DRAM density scales. See DDR SDRAM timing parameters.

Level 4 — Synthesis

Problem L4.1

The parent says leakage rises "roughly exponentially with temperature," and JEDEC halves $t_{R E F}$ from $64 ms$ to $32 ms$ above $8 5^{\circ} C$ . Model retention as $t_{r e t} \propto e^{+ E_{a} / k T}$ (higher $T$ → shorter retention). If retention halves between $4 5^{\circ} C$ and $8 5^{\circ} C$ , estimate the activation energy $E_{a}$ (in eV). Use $k = 8.617 \times 1 0^{- 5} eV/K$ .

Recall Solution

WHAT: find $E_{a}$ from a known ratio of retentions at two temperatures. WHY this tool: leakage currents follow an Arrhenius $\propto e^{- E_{a} / k T}$ law; retention (inverse of leakage) $\propto e^{+ E_{a} / k T}$ . Taking a ratio cancels the unknown prefactor — that's why we compare two temperatures instead of solving one. Convert to kelvin: $T_{1} = 45 + 273.15 = 318.15 K$ , $T_{2} = 85 + 273.15 = 358.15 K$ . Retention halves as $T$ rises: $\frac{t _{r e t} ( T _{2} )}{t _{r e t} ( T _{1} )} = \frac{1}{2}$ . $\frac{e ^{E_{a} / k T_{2}}}{e ^{E_{a} / k T_{1}}} = exp [\frac{E _{a}}{k} (\frac{1}{T _{2}} - \frac{1}{T _{1}})] = \frac{1}{2}$ $\frac{E _{a}}{k} (\frac{1}{T _{2}} - \frac{1}{T _{1}}) = ln \frac{1}{2} = - 0.6931.$ Compute the bracket: $\frac{1}{358.15} - \frac{1}{318.15} = 0.0027922 - 0.0031432 = - 3.510 \times 1 0^{- 4} K^{- 1}$ . $E_{a} = \frac{k \cdot ( - 0.6931 )}{- 3.510 \times 1 0 ^{- 4}} = \frac{( 8.617 \times 1 0 ^{- 5} ) ( - 0.6931 )}{- 3.510 \times 1 0 ^{- 4}} = 0.1702 eV .$ So $E_{a} \approx 0.17 eV$ — a modest barrier, consistent with junction leakage dominating. This is exactly why the $32 ms$ hot spec exists: retention roughly halves over that $4 0^{\circ}$ C span, so halving the period restores the safety margin.

Problem L4.2

Design check: you have a bank of $N = 32768$ rows. The weakest cell has measured retention $t_{r e t} = 52 ms$ . (a) Is the standard $64 ms$ period safe? (b) Choose the largest standard-style period that is safe and compute the resulting $t_{R I}$ .

Recall Solution

(a) The rule: $t_{R E F}$ must be less than the weakest cell's retention. Here $t_{r e t} = 52 ms < 64 ms$ , so $64 ms$ is NOT safe — that cell would drop below threshold before its turn came round. (b) Pick $t_{R E F} = 32 ms$ (the hot-spec value, and $< 52 ms$ with margin). $t_{R I} = \frac{32 \times 1 0 ^{- 3}}{32768} = 9.766 \times 1 0^{- 7} s \approx 0.977 μ s .$ WHY not just squeak in at, say, $50 ms$ ? Real designs want margin (temperature drift, aging, voltage droop), and standard timers use round values. $32 ms$ gives a comfortable $52/32 = 1.6 \times$ safety factor. Retention profiling (Low-power DRAM self-refresh, RAIDR) instead refreshes strong cells rarely and only the weak few often, recovering power.

Level 5 — Mastery

Problem L5.1

An engineer proposes cutting refresh power by refreshing at $128 ms$ instead of $64 ms$ , arguing "reads and writes already refresh their rows, so hot rows never actually decay." Under what workload does this fail, and estimate the worst-case exposure. Assume the weakest cell has exponential decay with $τ = 90 ms$ , $V_{t h} = V_{0} /2$ .

Recall Solution

WHAT could save power: it's true a normal activate/read restores that row (the sense amps re-drive full voltage — see Sense Amplifiers). So frequently accessed rows are effectively self-refreshing. WHERE it fails: a cold row — data written once and never touched (e.g. a rarely-read lookup table). It gets no incidental refresh, so it must survive on the REF schedule alone. Worst-case exposure: that cold cell's true retention is $t_{r e t} = τ ln \frac{V _{0}}{V _{t h}} = 90 \times ln 2 = 90 \times 0.6931 = 62.4 ms .$ With a $128 ms$ period, the cell can sit $128 - 62.4 = 65.6 ms$ past its safe window before the scheduled REF arrives — it decays below threshold and the bit is lost. Even the original $64 ms$ is borderline here ( $64 > 62.4$ !). So the proposal is unsafe; you'd need $t_{R E F} ≲ 62 ms$ , or per-row retention profiling to know which rows tolerate the long period. The deep lesson: "accesses refresh rows" is true on average but useless as a guarantee — the memory controller cannot assume any row is touched, so REF must cover the worst untouched cell. See Low-power DRAM self-refresh.

Problem L5.2

Full-stack calculation. A DDR bank: $N = 8192$ rows, $t_{R E F} = 64 ms$ , $t_{R F C} = 350 ns$ . During self-refresh (idle), the chip enters low-power mode where only refresh runs. If active-mode current draw for refresh is proportional to overhead, and the chip spends $70%$ of its life idle at $t_{R E F} = 64 ms$ and $30%$ hot-active at $t_{R E F} = 32 ms$ , compute the time-weighted average refresh overhead.

Recall Solution

Idle (cool) overhead: $t_{R F I} = 64 ms /8192 = 7.8125 μ s$ ; overhead $= 350/7812.5 = 4.48%$ . Hot-active overhead: $t_{R E F}$ halves to $32 ms$ , so $t_{R F I} = 32 ms /8192 = 3.90625 μ s$ ; overhead $= 350/3906.25 = 8.96%$ (double, because hot = twice as many REFs). Time-weighted average: $\overset{ˉ}{O} = 0.70 \times 4.48% + 0.30 \times 8.96% = 3.136% + 2.688% = 5.824% \approx 5.8%.$ WHY weight by time: overhead is a rate (fraction of each second lost); to get the lifetime average you weight each operating condition by the fraction of time spent in it. The hot mode, though only $30%$ of the time, contributes disproportionately because it refreshes twice as often — this is exactly the power motivation behind Low-power DRAM self-refresh and temperature-compensated refresh.

Recall Rapid self-test (click to reveal)

One-τ voltage fraction ::: $e^{- 1} \approx 37%$ of $V_{0}$ . Retention with $V_{t h} = V_{0} /2$ ::: $t_{r e t} = τ ln 2 \approx 0.693 τ$ . Refresh interval formula ::: $t_{R I} = t_{R E F} / N$ . Refresh overhead formula ::: $t_{R F C} / t_{R F I} = t_{R F C} N / t_{R E F}$ . Which cell sets the spec? ::: The single weakest (shortest-retention) cell on the chip. Why does exponential retain longer than linear (same $I_{0}$ )? ::: The resistive leak self-slows as $V$ drops; the linear drain never slows.

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