4.1.4 · D2Memory Technologies

Visual walkthrough — DRAM refresh and charge leakage

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This page is the picture-companion to the parent note. Every step here is one idea and one figure.


Step 1 — The bit is a puddle of charge on a capacitor

WHAT. A DRAM cell is one tiny capacitor (a charge-storage bucket) plus one transistor (a switch). We store a 1 by filling the bucket with charge, and a 0 by leaving it empty.

WHY start here. Every later symbol (, , ) is born on this picture. If we don't anchor them to the bucket now, the equations later will float free.

Let us define the three words we will use forever:

These three are tied together by the most basic capacitor law (see Capacitance Q=CV):

PICTURE. The bucket, its water level , and the little drip hole that will ruin everything.

Figure — DRAM refresh and charge leakage

Step 2 — Name the leak as a resistor

WHAT. The bucket has a slow drip. In electronics, "charge slowly escaping through something" is modelled as a resistor connecting the storage node to ground ().

WHY a resistor? Because a resistor is precisely "the component whose current is proportional to the voltage across it." A wider drip hole = a smaller resistance = a faster leak. This single number bundles together all three physical leak paths (subthreshold, junction, dielectric) into one handle we can do algebra with.

The escaping (leakage) current is therefore:

PICTURE. The same bucket, but now the drip hole is drawn as a resistor symbol, with the current arrow flowing out toward ground.

Figure — DRAM refresh and charge leakage

Step 3 — Bookkeeping: current out = charge lost per second

WHAT. We now write down the rate at which charge is disappearing. Whatever current leaves through the hole is exactly the charge the bucket loses each second.

WHY we need a rate. We want to know how the level changes over time. "How fast is something changing" is exactly the job of a derivative — that is why calculus enters here and nowhere earlier.

Charge conservation says the current out equals the drop in stored charge:

Term by term:

  • — the rate charge is leaving (minus sign: stored charge is going down).
  • , and is a fixed constant of the bucket, so we can pull it out: the charge rate is times the level rate.

PICTURE. Two arrows on the bucket: the current leaving through the hole, and the level ticking downward — the same event seen two ways.

Figure — DRAM refresh and charge leakage

Step 4 — Glue the two facts into one equation (an ODE)

WHAT. We have written the leak current two different ways. Step 2 said . Step 3 said . They are the same current, so set them equal. The result is an ODE — short for ordinary differential equation, meaning simply "an equation that links a quantity to its own rate of change."

WHY. This is the whole trick of physics: describe one thing from two angles, then equate. What pops out is a rule linking the level to its own rate of change.

Divide both sides by to isolate the rate:

Read this out loud: "the speed at which the level drops is proportional to how full the bucket still is." A near-full bucket drips fast; a near-empty one barely dribbles. That self-referential shape — rate of change proportional to current amount — is the fingerprint of exponential decay (the same maths as RC discharge and radioactive decay).

PICTURE. Three bucket snapshots — full, half, low — with the drip-rate arrow shrinking as the level drops.

Figure — DRAM refresh and charge leakage

Step 5 — Solve it: the exponential curve appears

WHAT. We solve the ODE from Step 4 for as an actual function of time — not by guessing, but by separating the variables and integrating.

WHY this method. Our equation mixes and together. The trick is to shove everything about to one side and everything about to the other, so each side can be integrated on its own. That is why "separation of variables" is the right tool: it untangles the two quantities.

The algebra, step by step. Start from Step 4 and gather -terms left, -terms right: Now integrate both sides — the left over , the right over : Here appears because the integral of is the natural logarithm, and is the integration constant fixed by the start. Raise to both sides to undo the : At the exponential is , so the leading constant must equal the starting level . Substituting gives the boxed result.

Define the combined constant that keeps appearing:

The solution:

Sanity checks (always test the ends):

  • At : , so . Correct — the bucket starts full.
  • As : , so . Correct — a fully-drained bucket, a lost bit.

PICTURE. The falling exponential curve with , the point at , and the tail approaching zero.

Figure — DRAM refresh and charge leakage

Step 6 — The deadline: retention time and the ½-full line

WHAT. The bit is not lost when the bucket empties — it is lost when the level sinks below the line the reader uses to tell 1 from 0. That line is the sense threshold , read by the sense amplifier, and it usually sits at half the full level, .

WHY half? The sense amp compares the cell against a reference sitting midway between a full 1 and an empty 0. Cross that midline and the amp guesses the wrong bit.

Set and solve for the time — call it the retention time :

To pull out of the exponent we need the tool that undoes : the natural logarithm . ( answers the question " to what power gives this number?") Taking of both sides and tidying signs:

With the standard , the ratio is , and :

PICTURE. The decay curve again, now with the dashed threshold line and the retention deadline marked where the curve crosses it.

Figure — DRAM refresh and charge leakage

Step 7 — The rule that follows: refresh before the deadline

WHAT. Refresh = re-fill the bucket before it crosses . You must revisit every cell within one refresh period , and you must pick

WHY the weakest cell. Different buckets have different-sized drip holes (manufacturing variation). One chip-wide period must satisfy the leakiest one. That is why the JEDEC number is even though a typical cell could hold for seconds.

Edge case — temperature. Heat widens every drip hole (leakage rises roughly like ), so falls, falls, and falls. Above about the spec halves to — the robot walks twice as fast (see Low-power DRAM self-refresh). This connects to the DDR timing .

PICTURE. Two decay curves (cool = slow, hot = fast) sharing the line, showing the hot cell hits the deadline sooner, forcing the walk.

Figure — DRAM refresh and charge leakage

The one-picture summary

Everything above, compressed: bucket → resistor leak → the ODE → the exponential → the threshold crossing → the refresh deadline.

Figure — DRAM refresh and charge leakage
Recall Feynman retelling — the whole walkthrough in plain words

A DRAM bit is water in a tiny bucket: full means 1, empty means 0. Every bucket has a slow drip. We called the drip hole a resistor so we could do maths on it, and we said the water escaping per second (a current) equals the drip. But that same escaping water is also the bucket's level dropping per second — so we wrote the leak two ways and set them equal. That gave one clean rule (an ordinary differential equation): the fuller the bucket, the faster it drips. Separating the and parts and integrating turns that rule into an exponential curve — starts at the full level, sinks toward empty. The reader (sense amp) can't tell 1 from 0 once the level dips past the half-full line, and the time to reach that line is the retention time, about where is the bucket's natural clock. So a robot must top up every bucket before its weakest member crosses that half-line — that top-up is refresh, standardized at , halved to when heat widens the holes.


Flashcards

Why does the exponential (not a straight line) describe DRAM decay?
Because the leak current is proportional to the remaining voltage (), and separating variables and integrating gives .
What does the time constant τ = R_leak·C physically mean?
The bucket's natural clock: time to fall to 1/e (~37%) of the start; big C (fat bucket) or big R_leak (thin hole) means slow forgetting.
Why must we take a natural log to find retention time?
To undo the exponential and isolate t from the exponent: ln answers "e to what power gives this ratio?" giving t_ret = τ·ln(V0/V_th).
Why is the refresh period set by the weakest cell?
Manufacturing variation gives cells different τ (leak rates); one chip-wide period must protect even the leakiest cell, so 64 ms is chosen with margin over the worst case.
Why does hot DRAM refresh at 32 ms instead of 64 ms?
Heat widens leakage (≈ e^(−Ea/kT)), lowering R_leak and τ, so retention time drops and the deadline arrives twice as fast.