Worked examples — DRAM refresh and charge leakage
Before we start, one promise: every symbol we use was earned in the parent note. Quick roll-call so you never scroll back —
Recall The symbols we will use (click to reveal)
::: capacitance of the storage cap (how much charge it holds per volt), from $Q=CV$. ::: the starting ("full bucket") voltage of a logic 1. ::: the sense-amp decision line; below it a 1 reads as 0. Usually . ::: an imaginary resistor modelling the leak to ground. ::: the RC time constant — the "natural clock" of the decay. ::: the leakage current draining the node (femtoamps). ::: retention time — how long before a full cell falls to . ::: the refresh period (whole chip must be revisited within this). Standard . (a.k.a. ) ::: refresh interval = gap between two REF commands. ::: how long one REF command ties up the bank.
The scenario matrix
Every question this topic can ask lands in one of these cells. The worked examples below each carry a [Cell X] tag so you can see the whole grid get filled.
| Cell | Case class | What makes it different | Example |
|---|---|---|---|
| A | Exponential decay, find | uses | Ex 1 |
| B | Linear / constant-current drain, half threshold | current is fixed, not | Ex 2 |
| C | Non-half threshold (exponential) | , log ≠ ln 2 | Ex 3 |
| B×C | Linear drain AND non-half threshold | general | Ex 3b |
| D | Refresh interval from row count | Ex 4 | |
| E | Real-world overhead word problem | busy ÷ interval, scaling | Ex 5 |
| F | Temperature corner (hot chip) | shrinks, period halves | Ex 6 |
| G | Degenerate: zero leakage | , never refresh | Ex 7 |
| H | Degenerate / exam twist: infinite leakage & weakest-cell logic | ; spec set by worst cell | Ex 8 |
Two decay pictures dominate everything — know when each applies:

Example 1 — Retention with a half-threshold [Cell A]
Forecast: guess — will it survive milliseconds, or seconds? (Jot a number before reading.)
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Compute . Why this step? is the decay's natural clock; every retention answer is times some pure number. We need it first. Why does come out in seconds? An ohm is volts-per-amp , and a farad is coulombs-per-volt . Multiply: . The volts and coulombs cancel, leaving pure seconds — so is genuinely a time.
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Recognise the threshold is exactly half. . Why this step? When , the log collapses: . No calculator gymnastics.
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Apply the retention formula (the boxed above). Why this step? This is the exact moment crosses the red decision line in the left panel of the figure (the curved resistor case).
Verify: Plug back into : . ✓ Exactly the threshold. Units: ms in, ms out. Since standard period, this cell is a borderline weak cell — refresh saves it.
Example 2 — Constant-current drain, half threshold [Cell B]
Forecast: will this be shorter or longer than the 41.6 ms of Ex 1? Guess.
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Charge to remove. We must lose worth of charge: Why this step? $Q=CV$ converts a voltage drop into the charge the current must carry away.
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Constant current ⇒ straight-line drain. Time = charge ÷ current: Why this step? With current fixed, — this is the straight ramp in the figure's right panel, not a curve.
Verify: Units: . ✓ And note it's way longer than Ex 1's 41.6 ms — because a real resistor drains fast while the voltage is high, whereas constant current is gentle throughout. Same cell, two models, two answers: always check which model the problem states.
Example 3 — A threshold that is NOT half (exponential) [Cell C]
Forecast: because the threshold is higher (closer to ), do we get more or less retention than the half case?
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Cannot use — the ratio isn't 2. Compute the true ratio: Why this step? The formula is general; only the special case simplifies to . Here we must take a real log.
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Apply the general formula. Why this step? , far less than .
Verify: Plug into : . ✓ And the lesson lands: a stricter (higher) threshold gives you LESS time — you demand the bit stay strong, so it fails sooner. Confirms the forecast: higher ⇒ shorter retention.
Example 3b — Constant current AND a non-half threshold [Cell B×C]
Forecast: the linear formula only cares about how many volts we drop, not the ratio — so will the "non-half" twist matter as much as it did in Example 3?
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Write the general linear-drain law. For constant current the drain is a straight line, so time is simply the charge lost over the current: Why this step? Unlike the exponential (which uses the ratio inside a log), the linear case uses the difference . Constant current removes charge at a fixed rate, so only the total charge removed matters — and that charge is by $Q=CV$.
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Plug the numbers. The drop is : Why this step? We're evaluating the straight-ramp crossing (right panel of the figure) for a shallow drop instead of a half drop.
Verify: Units: . ✓ Sanity: a smaller voltage window ( vs a half-drop of ) means less charge to lose, so a shorter time — consistent. And the forecast lands: in the linear case the non-half threshold enters as a simple difference , far tamer than the logarithm of a ratio it became in the exponential Example 3. Same twist, different model, different math.
Example 4 — Refresh interval from row count [Cell D]
Forecast: bigger than the parent's 8192 — will the interval be longer or shorter?
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Divide the budget evenly. Why this step? Distributed refresh spreads REFs uniformly over ; one every by definition.
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Evaluate. Why this step? Twice the rows as the parent's example ⇒ half the interval ().
Verify: Multiply back: . ✓ Units: ms ÷ (dimensionless count) = ms. Forecast confirmed: more rows ⇒ shorter interval (REFs fire faster).
Example 5 — Overhead scaling, a real-world twist [Cell E]
Forecast: true or false? Guess before computing.
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Overhead = busy time ÷ interval. Why this step? Every the bank is unusable for ; the fraction of time lost is that ratio.
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Evaluate. Why this step? Both in ns, so ratio is pure. — the vendor's claim is false for this large chip.
Verify: Sanity: 550 out of every 3906 ns busy → clearly more than a tenth, i.e. >10%. ✓ This is exactly the scaling wall the parent warned about: as chips grow, rises while stays , so overhead climbs toward 20%. This is why self-refresh and profiling schemes exist.
Example 6 — Hot chip corner [Cell F]
Forecast: if halves, does retention halve too? (Yes/no — think about the formula.)
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Retention is proportional to . ; the log factor is unchanged, only scales. Why this step? Temperature changes leakage, hence and — but not the voltage ratio. So retention scales linearly with .
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Halve it. Why this step? halved ⇒ retention halved. Direct proportionality.
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Compare to the period. ⇒ UNSAFE at the normal rate. Why this step? The refresh rule demands of the weakest cell. It now fails.
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JEDEC fix. Halve the period to (temperature-compensated self-refresh). Now ⇒ safe again. Why this step? This is precisely why hot DRAM refreshes twice as fast — the "robot walks twice as fast on a hot day."
Verify: Check the fix: ? ✓ Yes, margin restored. Forecast confirmed: retention does halve when halves.
Example 7 — Degenerate limit: zero leakage [Cell G]
Forecast: does a leak-free cell ever need refresh?
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Take the limit of . Why this step? is proportional to ; send resistance to infinity and the natural clock stops ticking.
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Retention explodes. . Why this step? Infinite times any finite log factor is infinite — the voltage in the figure never bends downward; it's a flat line forever.
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Refresh requirement. can be anything — refresh becomes unnecessary. Why this step? If the bit never decays below , there is nothing to top up.
Verify: This is the idealisation of SRAM — a static latch actively holds its bit and never needs refresh (at the cost of 6 transistors). ✓ The limit smoothly turns "dynamic" into "static". Sanity: flat line never crosses threshold ⇒ infinite retention. ✓
Example 8 — Infinite leakage & the weakest-cell exam twist [Cell H]
Forecast: for part (b), will the datasheet quote 200 ms or 50 ms? Why?
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(a) Restate the retention law for this cell. Since , the log is , so with . Why this step? We must anchor which formula applies before taking a limit; the half-threshold assumption is what turns the general log into .
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(a) Take . Why this step? Zero resistance ⇒ instant drain; the exponential collapses vertically. The bit is lost immediately — a dead cell.
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(a) Consequence. No finite can save it; it's a hard defect (mapped out by redundancy/repair, not refresh). Why this step? Refresh assumes the cell can hold charge between visits. If , refresh cannot keep up.
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(b) Datasheet uses the WEAKEST cell. The one 50 ms cell dictates the guarantee. A single period is quoted, and it must be strictly less than the worst retention: Why this step? The refresh rule is a worst-case guarantee: one lost bit corrupts data, so the whole chip runs at the pace of its slowest cell. A single number is published (not a range) — the standard picks the largest JEDEC-defined period that still sits safely under , which is the existing grade (the next standard step below ). Here , so it is safe with margin.
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(b) Over-refresh fraction. Almost every cell could safely wait but is forced to the pace: Why this step? Over-refresh = fraction of cells that could have waited longer than the quoted period but don't. Only the single weak cell truly needs 32 ms; all others are refreshed far more often than physics demands — pure wasted energy. This exact inefficiency is what retention-profiling (RAIDR) and self-refresh optimisations attack.
Verify: Part (a): . ✓ Part (b): the quoted period worst-case (safe with margin), and the over-refresh fraction — essentially all one billion cells. ✓ Forecast confirmed: the datasheet follows the 50 ms weakest cell (choosing the standard grade under it), never the 200 ms majority.
Recall One-line summary of every cell (click to reveal)
A: · B: (half) · C: · B×C: (general linear) · D: · E: overhead · F: hot ⇒ halves ⇒ period halves · G: ⇒ no refresh (SRAM-like) · H: ⇒ dead; datasheet follows weakest cell.